Renesas H8S Series Hardware Manual page 24

Section 1 Overview
Figure 1.1 Internal Block Diagram (HD64F2612, HD6432612, and HD6432611) ...............
Figure 1.2 Internal Block Diagram (HD6432616 and HD6432614) ......................................
Figure 1.3 Pin Arrangement (HD64F2612, HD6432612, and HD6432611) ..........................
Figure 1.4 Pin Arrangement (HD6432616 and HD6432614).................................................
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)............................................................... 17
Figure 2.2 Stack Structure in Normal Mode........................................................................... 17
Figure 2.3 Exception Vector Table (Advanced Mode)........................................................... 18
Figure 2.4 Stack Structure in Advanced Mode....................................................................... 19
Figure 2.5 Memory Map......................................................................................................... 20
Figure 2.6 CPU Registers ....................................................................................................... 21
Figure 2.7 Usage of General Registers ................................................................................... 22
Figure 2.8 Stack...................................................................................................................... 23
Figure 2.9 General Register Data Formats (1)........................................................................ 27
Figure 2.9 General Register Data Formats (2)........................................................................ 28
Figure 2.10 Memory Data Formats .......................................................................................... 29
Figure 2.11 Instruction Formats (Examples) ............................................................................ 41
Figure 2.12 Branch Address Specification in Memory Indirect Mode..................................... 45
Figure 2.13 State Transitions.................................................................................................... 49
Section 3 MCU Operating Modes
Figure 3.1 Address Map (H8S/2612, H8S/2611, H8S/2616, H8S/2614) ............................... 55
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled)......................... 60
Figure 4.2 Reset Sequence
(Advanced Mode with On-Chip ROM Disabled: Cannot be Used in this LSI) .... 61
Figure 4.3 Stack Status after Exception Handling .................................................................. 64
Figure 4.4 Operation when SP Value is Odd.......................................................................... 65
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller.................................................................. 68
Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5.......................................................... 75
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control
Mode 0 .................................................................................................................. 80
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 .............. 82
Rev. 6.00 Mar 15, 2006 page xxiv of xxxvi
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