Section 15 Controller Area Network (HCAN)
MCR5 = 1
Bus idle?
Initialize TEC and REC
Bus operation?
Yes
IRR12 = 1
IMR12 = 1?
Yes
Sleep mode clearing method
MCR7 = 0?
Yes (manual)
GSR3 = 1?
Yes
MCR5 = 0
11 recessive bits?
Yes
CAN bus communication possible
Rev. 6.00 Mar 15, 2006 page 428 of 570
REJ09B0211-0600
No
No
No
CPU interrupt
No (automatic)
Clear sleep mode?
Yes
No
GSR3 = 1?
Yes
MCR5 = 0
No
Figure 15.13 HCAN Sleep Mode Flowchart
MB should not be accessed
No
No
: Settings by user
: Processing by hardware