Figure 10.16 Example Of Buffer Operation (2) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Section 10 16-Bit Timer Pulse Unit (TPU)

2. When TGR is an input capture register

Figure 10.16 shows an operation example in which TGRA has been designated as an input

capture register, and buffer operation has been designated for TGRA and TGRC.

Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling

edges have been selected as the TIOCA pin input capture input edge.

As buffer operation has been set, when the TCNT value is stored in TGRA upon the

occurrence of input capture A, the value previously stored in TGRA is simultaneously

transferred to TGRC.

Rev. 6.00 Mar 15, 2006 page 208 of 570

REJ09B0211-0600

Figure 10.16 Example of Buffer Operation (2)