Figure 4.1 Reset Sequence (Advanced Mode With On-Chip Rom Enabled) - Renesas H8S Series Hardware Manual

Section 4 Exception Handling
φ
RES
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
(1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction

Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled)

Rev. 6.00 Mar 15, 2006 page 60 of 570
REJ09B0211-0600
Internal
Vector fetch
processing
(1) (3)
High
(2) (4)
Prefetch of first
program instruction
(5)
(6)