Renesas H8S Series Hardware Manual page 229

Bit Bit Name Initial value
3 TGFD 0
2 TGFC 0
Section 10 16-Bit Timer Pulse Unit (TPU)
R/W Description
R/(W) Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD
input capture or compare match in channels 0 and 3.
Only 0 can be written, for flag clearing. In channels 1,
2, 4, and 5, bit 3 is reserved. It is always read as 0
and cannot be modified.
[Setting conditions]
•
When TCNT = TGRD and TGRD is functioning as
output compare register
•
When TCNT value is transferred to TGRD by input
capture signal and TGRD is functioning as input
capture register
[Clearing conditions]
•
When DTC is activated by TGID interrupt and the
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFD after reading TGFD = 1
R/(W) Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC
input capture or compare match in channels 0 and 3.
Only 0 can be written, for flag clearing. In channels 1,
2, 4, and 5, bit 2 is reserved. It is always read as 0
and cannot be modified.
[Setting conditions]
•
When TCNT = TGRC and TGRC is functioning as
output compare register
•
When TCNT value is transferred to TGRC by input
capture signal and TGRC is functioning as input
capture register
[Clearing conditions]
•
When DTC is activated by TGIC interrupt and the
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFC after reading TGFC = 1
Rev. 6.00 Mar 15, 2006 page 193 of 570
REJ09B0211-0600