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Renesas H8S Series Hardware Manual page 597

16-bit single-chip microcomputer

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Register Name

Reset

TCR_5

Initialized

TMDR_5

Initialized

TIOR_5

Initialized

TIER_5

Initialized

TSR_5

Initialized

TCNTH_5

Initialized

TCNTL_5

Initialized

TGRAH_5

Initialized

TGRAL_5

Initialized

TGRBH_5

Initialized

TGRBL_5

Initialized

TSTR

Initialized

TSYR

Initialized

IPRA

Initialized

IPRB

Initialized

IPRC

Initialized

IPRD

Initialized

IPRE

Initialized

IPRF

Initialized

IPRG

Initialized

IPRH

Initialized

IPRJ

Initialized

IPRK

Initialized

IPRM

Initialized

RAMER

Initialized

P1DR

Initialized

PADR

Initialized

PBDR

Initialized

PCDR

Initialized

PDDR

Initialized

PFDR

Initialized

TCR_0

Initialized

TMDR_0

Initialized

TIORH_0

Initialized

TIORL_0

Initialized

TIER_0

Initialized

TSR_0

Initialized

TCNTH_0

Initialized

TCNTL_0

Initialized

TGRAH_0

Initialized

TGRAL_0

Initialized

TGRBH_0

Initialized

TGRBL_0

Initialized

TGRCH_0

Initialized

TGRCL_0

Initialized

TGRDH_0

Initialized

TGRDL_0

Initialized

Medium-

High-speed

speed

Sleep

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Software

Hardware

Module Stop

Standby

Standby

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Initialized

Rev. 6.00 Mar 15, 2006 page 561 of 570

Appendix

Module

TPU_5

TPU common

INT

ROM

PORT

TPU_0

REJ09B0211-0600

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