Renesas H8S Series Hardware Manual page 572

Appendix
Register Name
Interrupt priority register K
Interrupt priority register M
RAM emulation register
Port 1 data register
Port A data register
Port B data register
Port C data register
Port D data register
Port F data register
Timer control register_0
Timer mode register_0
Timer I/O control register H_0
Timer I/O control register L_0
Timer interrupt enable register_0
Timer status register_0
Timer counter H_0
Timer counter L_0
Timer general register AH_0
Timer general register AL_0
Timer general register BH_0
Timer general register BL_0
Timer general register CH_0
Timer general register CL_0
Timer general register DH_0
Timer general register DL_0
Timer control register_1
Timer mode register_1
Timer I/O control register_1
Timer interrupt enable register_1
Timer status register_1
Timer counter H_1
Timer counter L_1
Rev. 6.00 Mar 15, 2006 page 536 of 570
REJ09B0211-0600
Abbrevia-
Bit No. Address * Module
tion
IPRK 8
IPRM 8
RAMER 8
P1DR 8
PADR 8
PBDR 8
PCDR 8
PDDR 8
PFDR 8
TCR_0 8
TMDR_0 8
TIORH_0 8
TIORL_0 8
TIER_0 8
TSR_0 8
TCNTH_0 8
TCNTL_0 8
TGRAH_0 8
TGRAL_0 8
TGRBH_0 8
TGRBL_0 8
TGRCH_0 8
TGRCL_0 8
TGRDH_0 8
TGRDL_0 8
TCR_1 8
TMDR_1 8
TIOR_1 8
TIER_1 8
TSR_1 8
TCNTH_1 8
TCNTL_1 8
H'FECA INT
H'FECC INT
H'FEDB ROM
H'FF00 PORT
H'FF09 PORT
H'FF0A PORT
H'FF0B PORT
H'FF0C PORT
H'FF0E PORT
H'FF10 TPU_0
H'FF11 TPU_0
H'FF12 TPU_0
H'FF13 TPU_0
H'FF14 TPU_0
H'FF15 TPU_0
H'FF16 TPU_0
H'FF17 TPU_0
H'FF18 TPU_0
H'FF19 TPU_0
H'FF1A TPU_0
H'FF1B TPU_0
H'FF1C TPU_0
H'FF1D TPU_0
H'FF1E TPU_0
H'FF1F TPU_0
H'FF20 TPU_1
H'FF21 TPU_1
H'FF22 TPU_1
H'FF24 TPU_1
H'FF25 TPU_1
H'FF26 TPU_1
H'FF27 TPU_1
Data Access
Width State
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
8 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2