Renesas H8S Series Hardware Manual page 25

Figure 5.5 Interrupt Exception Handling................................................................................ 84
Figure 5.6 Contention between Interrupt Generation and Disabling ...................................... 87
Section 6 PC Break Controller (PBC)
Figure 6.1 Block Diagram of PC Break Controller ................................................................. 90
Figure 6.2 Operation in Power-Down Mode Transitions ........................................................ 93
Section 7 Bus Controller
Figure 7.1 On-Chip Memory Access Cycle............................................................................ 97
Figure 7.2 On-Chip Support Module Access Cycle ............................................................... 98
Figure 7.3 On-Chip HCAN Module Access Cycle (Wait States Inserted) ............................. 99
Figure 7.4 On-Chip MMT Module Access Cycle .................................................................. 100
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC ......................................................................................... 104
Figure 8.2 Block Diagram of DTC Activation Source Control .............................................. 110
Figure 8.3 Correspondence between DTC Vector Address and Register Information ........... 111
Figure 8.4 Flowchart of DTC Operation ................................................................................ 114
Figure 8.5 Memory Mapping in Normal Mode ...................................................................... 115
Figure 8.6 Memory Mapping in Repeat Mode ....................................................................... 116
Figure 8.7 Memory Mapping in Block Transfer Mode .......................................................... 118
Figure 8.8 Chain Transfer Operation...................................................................................... 119
Figure 8.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ................. 120
Figure 8.10 DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2)................................... 121
Figure 8.11 DTC Operation Timing (Example of Chain Transfer) .......................................... 121
Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.1 Block Diagram of TPU ......................................................................................... 162
Figure 10.2 Example of Counter Operation Setting Procedure ................................................ 197
Figure 10.3 Free-Running Counter Operation .......................................................................... 198
Figure 10.4 Periodic Counter Operation................................................................................... 199
Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match............ 199
Figure 10.6 Example of 0 Output/1 Output Operation ............................................................. 200
Figure 10.7 Example of Toggle Output Operation ................................................................... 200
Figure 10.8 Example of Input Capture Operation Setting Procedure ....................................... 201
Figure 10.9 Example of Input Capture Operation .................................................................... 202
Figure 10.10 Example of Synchronous Operation Setting Procedure ........................................ 203
Figure 10.11 Example of Synchronous Operation...................................................................... 204
Figure 10.12 Compare Match Buffer Operation......................................................................... 205
Figure 10.13 Input Capture Buffer Operation ............................................................................ 206
Rev. 6.00 Mar 15, 2006 page xxv of xxxvi