Receive Error Counter (Rec); Transmit Error Counter (Tec) - Renesas H8S Series Hardware Manual

Section 15 Controller Area Network (HCAN)
Bit Bit Name
7 to —
5
4 IMR12
3, 2 —
1 IMR9
0 IMR8

15.3.14 Receive Error Counter (REC)

The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating
the number of receive message errors on the CAN bus. The count value is stipulated in the CAN
protocol.

15.3.15 Transmit Error Counter (TEC)

The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter
indicating the number of transmit message errors on the CAN bus. The count value is stipulated in
the CAN protocol.
Rev. 6.00 Mar 15, 2006 page 406 of 570
REJ09B0211-0600
Initial Value R/W
All 1 R
1 R/W
All 1 R
1 R/W
1 R/W
Description
Reserved
These bits are always read as 1. Only 1 should be
written to these bits.
Bus Operation Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt
request by IRR12) is enabled. When set to 1,
OVR0 is masked.
Reserved
These bits are always read as 1. Only 1 should be
written to these bits.
Unread Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt
request by IRR9) is enabled. When set to 1, OVR0
is masked.
Mailbox Empty Interrupt Mask
When this bit is cleared to 0, SLE0 (interrupt
request by IRR8) is enabled. When set to 1, SLE0
is masked.