Transmit Wait Cancel Register (Txcr) - Renesas H8S Series Hardware Manual

15.3.6

Transmit Wait Cancel Register (TXCR)

The transmit wait cancel register (TXCR) is a 16-bit register that controls the cancellation of
transmit wait messages in mailboxes (buffers).
Bit Bit Name
15 TXCR7
14 TXCR6
13 TXCR5
12 TXCR4
11 TXCR3
10 TXCR2
9 TXCR1
8 —
7 TXCR15
6 TXCR14
5 TXCR13
4 TXCR12
3 TXCR11
2
TXCR10
1 TXCR9
0 TXCR8
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Section 15 Controller Area Network (HCAN)
Description
These bits cancel the transmit wait message in the
corresponding mailboxes 1 to 15. When TXCRn (n
= 1 to 15) is set to 1, the transmit wait message in
mailbox n is canceled.
[Clearing condition]
•
Completion of TXPR clearing when transmit
message is canceled normally
Bit 8 is reserved. This bit is always read as 0 and
the write value should always be 0.
Rev. 6.00 Mar 15, 2006 page 395 of 570
REJ09B0211-0600