Renesas H8S Series Hardware Manual page 34

Table 10.14 TIOR_1 (channel 1) ............................................................................................... 176
Table 10.15 TIOR_2 (channel 2) ............................................................................................... 177
Table 10.16 TIORH_3 (channel 3)............................................................................................. 178
Table 10.17 TIORL_3 (channel 3) ............................................................................................. 179
Table 10.18 TIOR_4 (channel 4) ............................................................................................... 180
Table 10.19 TIOR_5 (channel 5) ............................................................................................... 181
Table 10.20 TIORH_0 (channel 0)............................................................................................. 182
Table 10.21 TIORL_0 (channel 0) ............................................................................................. 183
Table 10.22 TIOR_1 (channel 1) ............................................................................................... 184
Table 10.23 TIOR_2 (channel 2) ............................................................................................... 185
Table 10.24 TIORH_3 (channel 3)............................................................................................. 186
Table 10.25 TIORL_3 (channel 3) ............................................................................................. 187
Table 10.26 TIOR_4 (channel 4) ............................................................................................... 188
Table 10.27 TIOR_5 (channel 5) ............................................................................................... 189
Table 10.28 Register Combinations in Buffer Operation........................................................... 205
Table 10.29 Cascaded Combinations ......................................................................................... 209
Table 10.30 PWM Output Registers and Output Pins................................................................ 212
Table 10.31 Phase Counting Mode Clock Input Pins................................................................. 216
Table 10.32 Up/Down-Count Conditions in Phase Counting Mode 1 ....................................... 218
Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2 ....................................... 219
Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 3 ....................................... 220
Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 4 ....................................... 221
Table 10.36 TPU Interrupts........................................................................................................ 224
Section 11 Motor Management Timer (MMT)
Table 11.1 Pin Configuration ................................................................................................... 247
Table 11.2 Initial Values of TBRU to TBRW and Initial Output............................................. 259
Table 11.3 MMT Interrupt Sources.......................................................................................... 263
Table 11.4 Pin Configuration ................................................................................................... 275
Section 12 Programmable Pulse Generator (PPG)
Table 12.1 PPG I/O Pins .......................................................................................................... 283
Section 13 Watchdog Timer
Table 13.1 WDT Interrupt Source............................................................................................ 309
Section 14 Serial Communication Interface (SCI)
Table 14.1 Pin Configuration ................................................................................................... 315
Table 14.2 Relationships between the N Setting in BRR and Bit Rate B ................................ 331
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) .................................. 332
Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ 334
Rev. 6.00 Mar 15, 2006 page xxxiv of xxxvi