Renesas H8S Series Hardware Manual page 18

12.4.1 Overview.............................................................................................................. 291
12.4.2 Output Timing...................................................................................................... 292
12.4.3 Sample Setup Procedure for Normal Pulse Output.............................................. 293
12.4.4 Example of Normal Pulse Output (Example of Five-Phase Pulse Output).......... 294
12.4.5 Non-Overlapping Pulse Output............................................................................ 295
12.4.6 Sample Setup Procedure for Non-Overlapping Pulse Output .............................. 297
12.4.7 Example of Non-Overlapping Pulse Output (Example of Four-Phase
Complementary Non-Overlapping Output) ......................................................... 298
12.4.8 Inverted Pulse Output .......................................................................................... 300
12.4.9 Pulse Output Triggered by Input Capture ............................................................ 301
12.5 Usage Notes ...................................................................................................................... 301
12.5.1 Module Stop Mode Setting .................................................................................. 301
12.5.2 Operation of Pulse Output Pins............................................................................ 301
Section 13 Watchdog Timer
13.1 Features ............................................................................................................................. 303
13.2 Register Descriptions ........................................................................................................ 304
13.2.1 Timer Counter (TCNT)........................................................................................ 304
13.2.2 Timer Control/Status Register (TCSR) ................................................................ 305
13.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 307
13.3 Operation .......................................................................................................................... 308
13.3.1 Watchdog Timer Mode ........................................................................................ 308
13.3.2 Interval Timer Mode ............................................................................................ 308
13.4 Interrupts ........................................................................................................................... 309
13.5 Usage Notes ...................................................................................................................... 309
13.5.1 Notes on Register Access..................................................................................... 309
13.5.2 Contention between Timer Counter (TCNT) Write and Increment ..................... 311
13.5.3 Changing Value of CKS2 to CKS0...................................................................... 311
13.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 311
13.5.5 Internal Reset in Watchdog Timer Mode............................................................. 312
13.5.6 OVF Flag Clearing in Intervel Timer Mode ........................................................ 312
Section 14 Serial Communication Interface (SCI)
14.1 Features ............................................................................................................................. 313
14.2 Input/Output Pins .............................................................................................................. 315
14.3 Register Descriptions ........................................................................................................ 315
14.3.1 Receive Shift Register (RSR) .............................................................................. 316
14.3.2 Receive Data Register (RDR) .............................................................................. 316
14.3.3 Transmit Data Register (TDR)............................................................................. 316
14.3.4 Transmit Shift Register (TSR) ............................................................................. 316
14.3.5 Serial Mode Register (SMR)................................................................................ 317
Rev. 6.00 Mar 15, 2006 page xviii of xxxvi
............................................................................................. 303
.................................................... 313