Operation; Overview; Figure 12.2 Ppg Output Operation - Renesas H8S Series Hardware Manual

12.4

Operation

12.4.1

Overview

Figure 12.2 shows a block diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in P1DDR and NDER are set to 1. An initial output value is determined by its
corresponding PODR initial setting. When the compare match event specified by PCR occurs, the
corresponding NDR bit contents are transferred to PODR to update the output values.
The sequential output of up to 8 bits of data is possible by writing new output data to NDR before
the next compare match.
Pulse output pin
Section 12 Programmable Pulse Generator (PPG)
DDR NDER
Q
Normal output/inverted output

Figure 12.2 PPG Output Operation

Q
Output trigger signal
C
PODR D Q NDR D
Rev. 6.00 Mar 15, 2006 page 291 of 570
Internal data bus
REJ09B0211-0600