Renesas H8S Series Hardware Manual page 22

18.5.3 Erase Block Register 1 (EBR1) ........................................................................... 464
18.5.4 Erase Block Register 2 (EBR2) ........................................................................... 465
18.5.5 RAM Emulation Register (RAMER)................................................................... 465
18.6 On-Board Programming Modes........................................................................................ 466
18.6.1 Boot Mode ........................................................................................................... 467
18.6.2 Programming/Erasing in User Program Mode..................................................... 469
18.7 Flash Memory Emulation in RAM ................................................................................... 471
18.8 Flash Memory Programming/Erasing ............................................................................... 473
18.8.1 Program/Program-Verify ..................................................................................... 473
18.8.2 Erase/Erase-Verify............................................................................................... 476
18.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 476
18.9 Program/Erase Protection ................................................................................................. 478
18.9.1 Hardware Protection ............................................................................................ 478
18.9.2 Software Protection.............................................................................................. 478
18.9.3 Error Protection.................................................................................................... 478
18.10 Programmer Mode ............................................................................................................ 479
18.11 Power-Down States for Flash Memory............................................................................. 479
18.12 Note on Switching from F-ZTAT Version to Mask ROM Version .................................. 480
Section 19 Clock Pulse Generator
19.1 Register Descriptions ........................................................................................................ 482
19.1.1 System Clock Control Register (SCKCR) ........................................................... 482
19.1.2 Low-Power Control Register (LPWRCR) ........................................................... 483
19.2 Oscillator........................................................................................................................... 484
19.2.1 Connecting a Crystal Resonator........................................................................... 484
19.2.2 External Clock Input ............................................................................................ 485
19.3 PLL Circuit ....................................................................................................................... 487
19.4 Medium-Speed Clock Divider .......................................................................................... 487
19.5 Bus Master Clock Selection Circuit .................................................................................. 487
19.6 Usage Notes ...................................................................................................................... 488
19.6.1 Note on Crystal Resonator ................................................................................... 488
19.6.2 Note on Board Design.......................................................................................... 488
Section 20 Power-Down Modes
20.1 Register Descriptions ........................................................................................................ 494
20.1.1 Standby Control Register (SBYCR) .................................................................... 494
20.1.2 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC)................... 496
20.2 Medium-Speed Mode........................................................................................................ 497
20.3 Sleep Mode ....................................................................................................................... 499
20.3.1 Transition to Sleep Mode..................................................................................... 499
20.3.2 Clearing Sleep Mode............................................................................................ 499
Rev. 6.00 Mar 15, 2006 page xxii of xxxvi
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