Register Configuration - Renesas H8S Series Hardware Manual

Section 8 Data Transfer Controller (DTC)
8.2

Register Configuration

The DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU.
When activated, the DTC reads a set of register information that is stored in on-chip RAM to the
corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated
register information back to the RAM.
• DTC enable registers (DTCER)
• DTC vector register (DTVECR)
For details on register addresses and register states during each process, refer to appendix A, On-
Chip I/O Register.
Rev. 6.00 Mar 15, 2006 page 105 of 570
REJ09B0211-0600