Interrupt Mask Register (Imr) - Renesas H8S Series Hardware Manual

15.3.13 Interrupt Mask Register (IMR)

The interrupt mask register (IMR) is a 16-bit register containing flags that enable or disable
requests by individual interrupt sources. The interrupt flag cannot be masked.
Bit Bit Name
15 IMR7
14 IMR6
13 IMR5
12 IMR4
11 IMR3
10 IMR2
9 IMR1
8 —
Initial Value R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
0 R
Section 15 Controller Area Network (HCAN)
Description
Overload Frame
When this bit is cleared to 0, OVR0 (interrupt
request by IRR7) is enabled. When set to 1, OVR0
is masked.
Bus Off Interrupt Mask
When this bit is cleared to 0, ERS0 (interrupt
request by IRR6) is enabled. When set to 1, ERS0
is masked.
Error Passive Interrupt Mask
When this bit is cleared to 0, ERS0 (interrupt
request by IRR5) is enabled. When set to 1, ERS0
is masked.
Receive Overload Warning Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt
request by IRR4) is enabled. When set to 1, OVR0
is masked.
Transmit Overload Warning Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt
request by IRR3) is enabled. When set to 1, OVR0
is masked.
Remote Frame Request Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt
request by IRR2) is enabled. When set to 1, OVR0
is masked.
Receive Message Interrupt Mask
When this bit is cleared to 0, RM1 (interrupt
request by IRR1) is enabled. When set to 1, RMI is
masked.
Reserved
This bit is always read as 0. Only 0 should be
written to this bit.
Rev. 6.00 Mar 15, 2006 page 405 of 570
REJ09B0211-0600