Figure 11.13 Buffer Operation Timing - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer
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Buffer Operation Timing: Figure 11.13 shows the compare match buffer operation timing.
φ
Compare match
signal
TCNT
TPDR
TPBR
TDDR
TGRUU, TGRVU,
TGRWU
TGRU, TGRV,
TGRW
TGRUD,
TGRVD, TGRWD
TBRU, TBRV,
TBRW
N − 1
N − 1
N
M0 + 2Td
M0
M1
L0 + 2Td
L0 + Td
L0
L0
L1

Figure 11.13 Buffer Operation Timing

Section 11 Motor Management Timer (MMT)
2Td + 1 2Td + 2
. . . .
2Td + 1
2Td
M1 + 2Td
M2
Td
L1 + 2Td
L1 + Td
L1
Rev. 6.00 Mar 15, 2006 page 267 of 570
M2 + 2Td
L2 + 2Td
L2 + Td
L2
L2
REJ09B0211-0600

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