Receive Data Sampling Timing And Reception Margin In Smart Card Interface Mode - Renesas H8S Series Hardware Manual

14.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface
Mode
In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372,
or 256 times the transfer rate (fixed at 16 times in normal asynchronous mode) as determined by
bits BCP1 and BCP0. In reception, the SCI samples the falling edge of the start bit using the basic
clock, and performs internal synchronization. As shown in figure 14.25, by sampling receive data
at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at
the middle of the bit. The reception margin is given by the following formula.
M = | (0.5 −
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
1
) − (L − 0.5) F −
2N
Section 14 Serial Communication Interface (SCI)
| D − 0.5 |
(1 + F) | × 100%
N
Rev. 6.00 Mar 15, 2006 page 367 of 570
REJ09B0211-0600