Renesas H8S Series Hardware Manual page 30

Figure 18.4 User Program Mode .............................................................................................. 459
Figure 18.5 Flash Memory Block Configuration...................................................................... 460
Figure 18.6 Programming/Erasing Flowchart Example in User Program Mode...................... 470
Figure 18.7 Flowchart for Flash Memory Emulation in RAM ................................................. 471
Figure 18.8 Example of RAM Overlap Operation ................................................................... 472
Figure 18.9 Program/Program-Verify Flowchart ..................................................................... 475
Figure 18.10 Erase/Erase-Verify Flowchart ............................................................................... 477
Section 19 Clock Pulse Generator
Figure 19.1 Block Diagram of Clock Pulse Generator ............................................................. 481
Figure 19.2 Connection of Crystal Resonator (Example)......................................................... 484
Figure 19.3 Crystal Resonator Equivalent Circuit.................................................................... 484
Figure 19.4 External Clock Input (Examples) .......................................................................... 485
Figure 19.5 External Clock Input Timing................................................................................. 486
Figure 19.6 Note on Board Design of Oscillator Circuit .......................................................... 488
Figure 19.7 External Circuitry Recommended for PLL Circuit ............................................... 489
Section 20 Power-Down Modes
Figure 20.1 Mode Transition Diagram ..................................................................................... 492
Figure 20.2 Medium-Speed Mode Transition and Clearance Timing ...................................... 498
Figure 20.3 Software Standby Mode Application Example ..................................................... 502
Figure 20.4 Timing of Transition to Hardware Standby Mode ................................................ 503
Figure 20.5 Timing of Recovery from Hardware Standby Mode............................................. 504
Section 21 Electrical Characteristics
Figure 21.1 Output Load Circuit .............................................................................................. 511
Figure 21.2 System Clock Timing............................................................................................ 512
Figure 21.3 Oscillation Stabilization Timing ........................................................................... 513
Figure 21.4 Reset Input Timing................................................................................................ 514
Figure 21.5 Interrupt Input Timing........................................................................................... 514
Figure 21.6 I/O Port Input/Output Timing ............................................................................... 516
Figure 21.7 TPU Input/Output Timing ..................................................................................... 517
Figure 21.8 TPU Clock Input Timing....................................................................................... 517
Figure 21.9 SCK Clock Input Timing ...................................................................................... 517
Figure 21.10 SCI Input/Output Timing (Clock Synchronous Mode) ......................................... 518
Figure 21.11 A/D Converter External Trigger Input Timing ..................................................... 518
Figure 21.12 HCAN Input/Output Timing ................................................................................. 518
Figure 21.13 PPG Output Timing............................................................................................... 518
Figure 21.14 MMT Input/Output Timing ................................................................................... 519
Figure 21.15 POE Input/Output Timing ..................................................................................... 519
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