Figure 2.3 Exception Vector Table (Advanced Mode) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Table of Contents

Section 2 CPU

• Instruction Set

All instructions and addressing modes can be used.

• Exception Vector Table and Memory Indirect Branch Addresses

In advanced mode, the top area starting at H'00000000 is allocated to the exception vector

table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is

stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4,

Exception Handling.

Figure 2.3 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions

uses an 8-bit absolute address included in the instruction code to specify a memory operand

that contains a branch address. In advanced mode the operand is a 32-bit longword operand,

providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is

regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.

Note that the first part of this range is also the exception vector table.

Rev. 6.00 Mar 15, 2006 page 18 of 570

REJ09B0211-0600

Exception vector 1

Exception vector 2

Exception vector 3

Exception vector 4

Exception vector 5

Exception vector table