Renesas H8S Series Hardware Manual page 29

Figure 14.32 Clock Halt and Restart Procedure ......................................................................... 375
Figure 14.33 Sample Transmission using DTC in Clocked Synchronous Mode........................ 379
Figure 14.34 Sample Flowchart for Mode Transition during Transmission............................... 380
Figure 14.35 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............ 380
Figure 14.36 Pin States during Transmission in Clocked Synchronous Mode
(Internal Clock) ..................................................................................................... 381
Figure 14.37 Sample Flowchart for Mode Transition during Reception .................................... 382
Figure 14.38 Operation when Switching from SCK Pin to Port Pin .......................................... 383
Section 15 Controller Area Network (HCAN)
Figure 15.1 HCAN Block Diagram .......................................................................................... 386
Figure 15.2 Message Control Register Configuration .............................................................. 411
Figure 15.3 Standard Format .................................................................................................... 411
Figure 15.4 Extended Format ................................................................................................... 411
Figure 15.5 Message Data Configuration ................................................................................. 413
Figure 15.6 Hardware Reset Flowchart .................................................................................... 416
Figure 15.7 Software Reset Flowchart ..................................................................................... 417
Figure 15.8 Detailed Description of One Bit............................................................................ 418
Figure 15.9 Transmission Flowchart ........................................................................................ 421
Figure 15.10 Transmit Message Cancellation Flowchart ........................................................... 423
Figure 15.11 Reception Flowchart ............................................................................................. 424
Figure 15.12 Unread Message Overwrite Flowchart.................................................................. 427
Figure 15.13 HCAN Sleep Mode Flowchart .............................................................................. 428
Figure 15.14 HCAN Halt Mode Flowchart ................................................................................ 430
Figure 15.15 DTC Transfer Flowchart ....................................................................................... 432
Figure 15.16 High-Speed Interface Using PCA82C250............................................................. 433
Section 16 A/D Converter
Figure 16.1 Block Diagram of A/D Converter ......................................................................... 438
Figure 16.2 A/D Conversion Timing........................................................................................ 445
Figure 16.3 External Trigger Input Timing .............................................................................. 447
Figure 16.4 A/D Conversion Precision Definitions.................................................................. 449
Figure 16.5 A/D Conversion Precision Definitions.................................................................. 449
Figure 16.6 Example of Analog Input Circuit .......................................................................... 450
Figure 16.7 Example of Analog Input Protection Circuit......................................................... 452
Figure 16.8 Analog Input Pin Equivalent Circuit ..................................................................... 452
Section 18 ROM
Figure 18.1 Block Diagram of Flash Memory.......................................................................... 456
Figure 18.2 Flash Memory State Transitions............................................................................ 457
Figure 18.3 Boot Mode............................................................................................................. 458
Rev. 6.00 Mar 15, 2006 page xxix of xxxvi