Section 15 Controller Area Network (HCAN)
IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery
from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are
enabled, IRR0 should be cleared.
MCR0 = 1 (automatic)
IRR0 = 1 (automatic)
GSR3 = 1 (automatic)
Initialization of HCAN module
Mailbox initialization
Message transmission method initialization
IMR setting (interrupt mask setting)
MBIMR setting (interrupt mask setting)
MC[x] setting (receive identifier setting)
LAFM setting (receive identifier mask setting)
recessive bits received?
Can bus communication enabled
Rev. 6.00 Mar 15, 2006 page 416 of 570
REJ09B0211-0600
Hardware reset
Clear IRR0
BCR setting
MBCR setting
MCR0 = 0
GSR3 = 0?
Yes
GSR3 = 0 & 11
Yes
Figure 15.6 Hardware Reset Flowchart
: Settings by user
: Processing by hardware
Bit configuration mode
Period in which BCR, MBCR, etc.,
are initialized
No
No