Renesas H8S Series Hardware Manual page 33

Table 8.4 Register Information in Block Transfer Mode ....................................................... 117
Table 8.5 DTC Execution Status ............................................................................................ 122
Table 8.6 Number of States Required for Each Execution Status .......................................... 122
Section 9 I/O Ports
Table 9.1 Port Functions ........................................................................................................ 128
Table 9.2 P17 Pin Function .................................................................................................... 132
Table 9.3 P16 Pin Function ................................................................................................... 132
Table 9.4 P15 Pin Function .................................................................................................... 133
Table 9.5 P14 Pin Function ................................................................................................... 133
Table 9.6 P13 Pin Function .................................................................................................... 133
Table 9.7 P12 Pin Function .................................................................................................... 134
Table 9.8 P11 Pin Function .................................................................................................... 134
Table 9.9 P10 Pin Function .................................................................................................... 134
Table 9.10 PA3 Pin Function ................................................................................................... 140
Table 9.11 PA2 Pin Function ................................................................................................... 140
Table 9.12 PA1 Pin Function ................................................................................................... 140
Table 9.13 PA0 Pin Function ................................................................................................... 140
Table 9.14 PB7 Pin Function ................................................................................................... 144
Table 9.15 PB6 Pin Function ................................................................................................... 144
Table 9.16 PB5 Pin Function ................................................................................................... 145
Table 9.17 PB4 Pin Function ................................................................................................... 145
Table 9.18 PB3 Pin Function ................................................................................................... 145
Table 9.19 PB2 Pin Function ................................................................................................... 146
Table 9.20 PB1 Pin Function ................................................................................................... 146
Table 9.21 PB0 Pin Function ................................................................................................... 146
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.1 TPU Functions........................................................................................................ 160
Table 10.2 TPU Pins ................................................................................................................ 163
Table 10.3 CCLR0 to CCLR2 (channels 0 and 3).................................................................... 167
Table 10.4 CCLR0 to CCLR2 (channels 1, 2, 4, and 5)........................................................... 167
Table 10.5 TPSC0 to TPSC2 (channel 0)................................................................................. 168
Table 10.6 TPSC0 to TPSC2 (channel 1)................................................................................. 168
Table 10.7 TPSC0 to TPSC2 (channel 2)................................................................................. 169
Table 10.8 TPSC0 to TPSC2 (channel 3)................................................................................. 169
Table 10.9 TPSC0 to TPSC2 (channel 4)................................................................................. 170
Table 10.10 TPSC0 to TPSC2 (channel 5)................................................................................. 170
Table 10.11 MD0 to MD3.......................................................................................................... 172
Table 10.12 TIORH_0 (channel 0)............................................................................................. 174
Table 10.13 TIORL_0 (channel 0) ............................................................................................. 175
Rev. 6.00 Mar 15, 2006 page xxxiii of xxxvi