1.1
Overview
• High-speed H8S/2600 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
69 basic instructions
• Various peripheral functions
PC break controller
Data transfer controller (DTC)
16-bit timer-pulse unit (TPU)
Motor management timer (MMT)
Programmable pulse generator (PPG)
Watchdog timer
Asynchronous or clocked synchronous serial communication interface (SCI)
Controller area network (HCAN)
10-bit A/D converter
Clock pulse generator
• On-chip memory
ROM
F-ZTAT version
Mask ROM
version
• General I/O ports
I/O pins: 43
Input-only pins: 13
• Supports various power-down states
Section 1 Overview
Model
ROM
HD64F2612
128 kbytes
HD6432612
128 kbytes
HD6432611
64 kbytes
HD6432616
128 kbytes
HD6432614
64 kbytes
Section 1 Overview
RAM
Remarks
4 kbytes
4 kbytes
4 kbytes
4 kbytes
4 kbytes
Rev. 6.00 Mar 15, 2006 page 1 of 570
REJ09B0211-0600