Figure 11.15 Timing Of Status Flag Clearing By Cpu; Figure 11.16 Timing Of Status Flag Clearing By Dtc Controller - Renesas H8S Series Hardware Manual

Status Flag Clearing Timing: A status flag is cleared when the CPU reads 1 from the flag, then 0
is written to it. When the DTC controller is activated, the flag is cleared automatically. Figure
11.15 shows the timing of status flag clearing by the CPU, and figure 11.16 shows the timing of
status flag clearing by the DTC.
φ
Address
Write signal
Status flag
TGI interrupt

Figure 11.15 Timing of Status Flag Clearing by CPU

φ
Address
Status flag
TGI interrupt

Figure 11.16 Timing of Status Flag Clearing by DTC Controller

Section 11 Motor Management Timer (MMT)
TSR write cycle
T T T
1 2 3
TSR address
DTC
read cycle write cycle
T T T T
1 2 3 1
Source address Destination address
Rev. 6.00 Mar 15, 2006 page 269 of 570
DTC
T T
2 3
REJ09B0211-0600