Renesas H8S Series Hardware Manual page 32

Section 1 Overview
Table 1.1 Comparison of Product Specifications ................................................................... 12
Section 2 CPU
Table 2.1 Instruction Classification........................................................................................ 30
Table 2.2 Operation Notation................................................................................................. 31
Table 2.3 Data Transfer Instructions ...................................................................................... 32
Table 2.4 Arithmetic Operations Instructions ........................................................................ 33
Table 2.5 Logic Operations Instructions ................................................................................ 35
Table 2.6 Shift Instructions .................................................................................................... 35
Table 2.7 Bit Manipulation Instructions................................................................................. 36
Table 2.8 Branch Instructions ................................................................................................ 38
Table 2.9 System Control Instructions ................................................................................... 39
Table 2.10 Block Data Transfer Instructions ........................................................................... 40
Table 2.11 Addressing Modes.................................................................................................. 42
Table 2.12 Absolute Address Access Ranges .......................................................................... 44
Section 3 MCU Operating Modes
Table 3.1 MCU Operating Mode Selection............................................................................ 51
Table 3.2 Pin Functions in Each Mode .................................................................................. 54
Section 4 Exception Handling
Table 4.1 Exception Types and Priority ................................................................................. 57
Table 4.2 Exception Handling Vector Table .......................................................................... 58
Table 4.3 Status of CCR and EXR after Trace Exception Handling ...................................... 62
Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling ..................... 63
Section 5 Interrupt Controller
Table 5.1 Pin Configuration ................................................................................................... 69
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................ 77
Table 5.3 Interrupt Control Modes......................................................................................... 79
Table 5.4 Interrupt Response Times....................................................................................... 85
Table 5.5 Number of States in Interrupt Handling Routine Execution Status........................ 86
Section 8 Data Transfer Controller (DTC)
Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ................ 112
Table 8.2 Register Information in Normal Mode ................................................................... 115
Table 8.3 Register Information in Repeat Mode .................................................................... 116
Rev. 6.00 Mar 15, 2006 page xxxii of xxxvi
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