Input/Output Pins; Register Descriptions; Table 11.4 Pin Configuration - Renesas H8S Series Hardware Manual

11.8.2

Input/Output Pins

Table 11.4 shows the pin configuration of the POE circuit.

Table 11.4 Pin Configuration

Name
Port output enable input pins
11.8.3

Register Descriptions

The POE circuit has the following registers. The ICSR registers are initialized by a reset or in
hardware standby mode. However, they are not initialized in software standby mode or sleep mode
and retain their previous values. For details on register addresses, refer to appendix A, On-Chip
I/O Register.
• Input level control/status register (ICSR)
• POE pin control register (POEPC)
Input Level Control/Status Register (ICSR) : The input level control/status register (ICSR) is a
16-bit readable/writable register that selects the input mode for pins POE0 to POE3, controls
enabling or disabling of interrupts, and holds status information.
Bit Bit Name Initial Value
15 POE3F 0
Section 11 Motor Management Timer (MMT)
Abbreviation I/O
POE0 to POE3 Input
R/W Description
R/(W) *
POE3 Flag
Indicates that a high impedance request has been
input to the POE3 pin.
[Clearing condition]
•
When 0 is written to POE3F after reading
POE3F = 1
[Setting condition]
•
When the input set by bits 6 and 7 of ICSR
occurs at the POE3 pin
Function
Input request signals for placing
MMT's output pins in high-impedance
state
Rev. 6.00 Mar 15, 2006 page 275 of 570
REJ09B0211-0600