Figure 11.7 Example Of Tcnt Counter Clearing - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Section 11 Motor Management Timer (MMT)

At the falling edge of PCI, the TCNT counter is cleared to 2Td (initial set value), counts up until it

reaches the TPDR value, and then starts counting down. When the count reaches 2Td, TCNT starts

counting up again, and this sequence is repeated. An example of counter clearing is shown in

figure 11.7.

(counter clear input)

Figure 11.7 Example of TCNT Counter Clearing

Toggle Output Synchronized with PWM Period: In the operating modes, output can be toggled

synchronously with the PWM carrier period. When outputting the PWM period, the PCO pin

function should be set to output using the MMT pin control register. An example of the toggle

output waveform is shown in figure 11.8.

PWM output is toggled according to the TCNT count direction. The toggle output pin is PCO.

PCO outputs 1 when TCNT is counting up, and 0 when counting down.

Output State when Counter is Halted: When TCNT is halted, the state of the PWM outputpin is

retained. The TCNT value is also retained.

Rev. 6.00 Mar 15, 2006 page 261 of 570

REJ09B0211-0600