Port D Data Register (Pddr); Port D Register (Portd) - Renesas H8S Series Hardware Manual

9.7.2

Port D Data Register (PDDR)

PDDR is an 8-bit readable/writable register that stores output data for the port D pins.
Bit Bit Name
7 PD7DR
6 PD6DR
5 PD5DR
4 PD4DR
3 PD3DR
2 PD2DR
1 PD1DR
0 PD0DR
9.7.3

Port D Register (PORTD)

PORTD is an 8-bit read-only register that shows port D pin states.
PORTD cannot be modified.
Bit Bit Name
7 PD7
6 PD6
5 PD5
4 PD4
3 PD3
2 PD2
1 PD1
0 PD0
Note: * Determined by the states of pins PD7 to PD0.
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
Undefined *
R
Undefined *
R
Undefined *
R
Undefined *
R
Undefined *
R
Undefined *
R
Undefined *
R
Undefined *
R
Description
Output data for a pin is stored when the pin is
specified as a general purpose I/O port.
Description
If a port D read is performed while PDDDR bits are
set to 1, the PDDR values are read. If a port D read
is performed while PDDDR bits are cleared to 0, the
pin states are read.
Rev. 6.00 Mar 15, 2006 page 153 of 570
Section 9 I/O Ports
REJ09B0211-0600