Port Output Enable (Poe); Features; Figure 11.21 Block Diagram Of Poe - Renesas H8S Series Hardware Manual

Section 11 Motor Management Timer (MMT)
11.8

Port Output Enable (POE)

The port output enable (POE) circuit enables the MMT's output pins (POUA, POUB, POVA,
POVB, POWA, POWB, and PCO) to be placed in the high-impedance state by varying the input
at pins POE0 to POE3. An interrupt can also be requested at the same time.
11.8.1

Features

The POE circuit has the following features:
• Falling edge, φ/8 × 16 times, φ/16 × 16 times, or φ/128 × 16 times low-level sampling can be
set for each of input pins POE0 to POE3.
• The MMT's output pins can be placed in the high-impedance state on sampling of a falling
edge or low level at pins POE0 to POE3.
• An interrupt request can be initiated by input level sampling.
Input level detection circuit
POE3
POE2
POE1
POE0
Rev. 6.00 Mar 15, 2006 page 274 of 570
REJ09B0211-0600
ICSR
Falling edge
detection circuit
Low level
detection circuit
φ/128
φ/8 φ/16
Frequency divider
φ

Figure 11.21 Block Diagram of POE

High impedance request
control signal
Interrupt request