Figure 15.10 Transmit Message Cancellation Flowchart - Renesas H8S Series Hardware Manual

can be requested, and if the mailbox empty interrupt (IRR8) is enabled for the bits (MBIMR1 to
MBIMR15) corresponding to the mailbox interrupt mask register (MBIMR) and interrupt mask
register (IMR), interrupts may be sent to the CPU.
However, a transmit wait message cannot be canceled at the following times:
• During internal arbitration or CAN bus arbitration
• During data frame or remote frame transmission
Figure 15.10 shows a flowchart for transmit message cancellation.
Message transmit wait TXPR setting
Set TXCR bit corresponding to
End of transmission/transmission

Figure 15.10 Transmit Message Cancellation Flowchart

message to be canceled
Cancellation possible?
Yes
Message not sent
Clear TXCR, TXPR
ABACK = 1
IRR8 = 1
IMR8 = 1?
No
Interrupt to CPU
Clear TXACK
Clear ABACK
Clear IRR8
cancellation
Section 15 Controller Area Network (HCAN)
: Settings by user
: Processing by hardware
No
Completion of message transmission
TXACK = 1
Clear TXCR, TXPR
IRR8 = 1
Yes
Rev. 6.00 Mar 15, 2006 page 423 of 570
REJ09B0211-0600