Table 10.17 Tiorl_3 (Channel 3) - Renesas H8S Series Hardware Manual

Table 10.17 TIORL_3 (channel 3)

Bit 7 Bit 6 Bit 5
IOD3 IOD2 IOD1
0 0 0
1
1 0
1
1 0 0
1
1 X
Legend:
X: Don't care
Notes: 1. When bits TPSC0 to TPSC2 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Bit 4 TGRD_3
IOD0 Function
0 Output
compare
1
register *
2
0
1
0
1
0
1
0 Input
capture
1
register * 2
X
X
Section 10 16-Bit Timer Pulse Unit (TPU)
Description
TIOCD_3 Pin Function
Output disabled
Initial output is 0
0 output at compare match
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
Output disabled
Initial output is 1
0 output at compare match
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down *
Rev. 6.00 Mar 15, 2006 page 179 of 570
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REJ09B0211-0600