Interrupts; Table 15.4 Hcan Interrupt Sources - Renesas H8S Series Hardware Manual

15.5

Interrupts

Table 15.4 lists the HCAN interrupt sources. With the exception of the reset processing vector
(IRR0), these sources can be masked. Masking is implemented using the mailbox interrupt mask
register (MBIMR) and interrupt mask register (IMR). For details on the interrupt vector of each
interrupt source, refer to section 5, Interrupt Controller.

Table 15.4 HCAN Interrupt Sources

Name Description
Error passive interrupt (TEC ≥ 128 or REC ≥ 128)
ERS0/OVR0
Bus off interrupt (TEC ≥ 256)
Reset process interrupt by power-on reset
Remote frame reception
Error warning interrupt (TEC ≥ 96)
Error warning interrupt (REC ≥ 96)
Overload frame transmission interrupt
Unread message overwrite
Detection of CAN bus operation in HCAN sleep mode
RM0 Mailbox 0 message reception
RM1 Mailboxes 1 to 15 message reception
SLE0 Message transmission/cancellation
Section 15 Controller Area Network (HCAN)
Interrupt
Flag
IRR5
IRR6
IRR0
IRR2
IRR3
IRR4
IRR7
IRR9
IRR12
IRR1
IRR1
IRR8
Rev. 6.00 Mar 15, 2006 page 431 of 570
DTC
Activation
Not
possible
Possible
Not
possible
Not
possible
REJ09B0211-0600