Renesas H8S Series Hardware Manual page 342

Section 13 Watchdog Timer
Bit Bit Name Initial Value
2 CKS2 0
1 CKS1 0
0 CKS0 0
Note: * Only 0 can be written, for flag clearing.
Rev. 6.00 Mar 15, 2006 page 306 of 570
REJ09B0211-0600
R/W Description
R/W Clock Select 0 to 2
R/W Selects the clock source to be input to TCNT. The
overflow frequency for φ = 20 MHz is enclosed in
R/W
parentheses.
000: Clock φ/2 (frequency: 25.6 µs)
001: Clock φ/64 (frequency: 819.2 µs)
010: Clock φ/128 (frequency: 1.6 ms)
011: Clock φ/512 (frequency: 6.6 ms)
100: Clock φ/2048 (frequency: 26.2 ms)
101: Clock φ/8192 (frequency: 104.9 ms)
110: Clock φ/32768 (frequency: 419.4 ms)
111: Clock φ/131072 (frequency: 1.68 s)