Renesas H8S Series Hardware Manual page 8

Item
11.8.3 Register
Descriptions
14.3.9 Bit Rate
Register (BRR)
Table 14.2
Relationships between
the N Setting in BRR
and Bit Rate B
14.9.7 Notes when
Switching from SCK
Pin to Port Pin
15.3.20 HCAN
Monitor Register
(HCANMON)
18.2 Module
Transitions
Figure 18.2 Flash
Memory State
Transitions
18.9.3 Error
Protection
Rev. 6.00 Mar 15, 2006 page viii of xxxvi
Page Revision (See Manual for Details)
277, Bit 7 to 0 description of Input level control/status register
278 amended
(Before) Pφ/8 clock → (After) φ/8 clock
(Before) Pφ/16 clock → (After) φ/16 clock
(Before) Pφ/128 clock → (After) φ/128 clock
331 Table 14.2 amended
Mode
Asynchronous
Mode
Clocked
Synchronous
Mode
Smart Card
Interface Mode
382 Problem in Operation
Description amended
(Before) C/A → (After) C/A
414 Table amended
Bit Bit Name
7 to —
2
457 Figure 18.2 amended
(Before) RES = 0 → (After) RES = 0
479 Description amended
... However, PV1 and EV1 bit setting is enabled, and a
transition can be made to verify mode. ...
Bit Rate Error
φ × 10
6
B = Error (%) = {
64 × 2 × (N + 1)
2n-1
—
φ × 10
6
B =
8 × 2 × (N + 1)
2n-1
φ × 10
6
B = Error (%) = {
S × 2 × (N + 1)
2n+1
Initial Value R/W Description
Undefined — Reserved
Only 0 should be written to these bits.
φ × 10
6
− 1 } × 100
B × 64 × 2 × (N + 1)
2n-1
φ × 10
6
− 1 } × 100
B × S × 2 × (N + 1)
2n+1