Renesas H8S Series Hardware Manual page 324

Section 12 Programmable Pulse Generator (PPG)
If pulse output groups 0 and output pulse groups 1 have different output triggers, upper 4 bits and
lower 4 bits are mapped to the different addresses as shown below.
Bit Bit Name
7 NDR7
6 NDR6
5 NDR5
4 NDR4
3 to —
0
Bit Bit Name
7 to —
4
3 NDR3
2 NDR2
1 NDR1
0 NDR0
Rev. 6.00 Mar 15, 2006 page 288 of 570
REJ09B0211-0600
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
All 1 —
Initial Value R/W
All 1 —
0 R/W
0 R/W
0 R/W
0 R/W
Description
Next Data Register 4 to 7
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Reserved
These bits are always read as 1 and cannot be
modified.
Description
Reserved
1 is always read and write is disabled.
Next Data Register 3 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.