Figure 18.9 Program/Program-Verify Flowchart - Renesas H8S Series Hardware Manual

Write pulse application subroutine
Apply Write Pulse
WDT enable
Set PSU bit in FLMCR1
) µs
Wait (t
spsu
Set P bit in FLMCR1
) µs
Wait (t
sp
Clear P bit in FLMCR1
) µs
Wait (t
cp
Clear PSU bit in FLMCR1
) µs
Wait (t
cpsu
Disable WDT
End Sub
Note: 6. Write Pulse Width
Write Time (tsp) µs
Number of Writes n
1
2
3
4
5
6
7
8
9
10
11
12
13
998
999
1000
Note: * Use a 10 µs write pulse for additional programming.
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area
(128 bytes)
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written
to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer
than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between
the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are programmed in the next reprogramming loop.
Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
5. A write pulse of 30 s or 200 µs is applied according to the progress of the programming operation. See note 6 for details of the pulse widths.
When writing of additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
7. The wait times and value of N are shown in section 21.5, Flash Memory characteristics.
Reprogram Data Computation Table
Original Data Verify Data Reprogram Data
(D) (V) (X)
0 0 1
0 1 0
1 0 1
1 1 1

Figure 18.9 Program/Program-Verify Flowchart

* 7
Start of programming
5 7
* *
End of programming
* 7
* 7
Increment address
*
30
*
30
*
30
*
30
*
30
*
30
200
200
200
200
200
200
200
200
200
200
Comments
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Start of programming
START
Set SWE bit in FLMCR1
) µs
Wait (t
sswe
Store 128-byte program data in program
data area and reprogram data area
n = 1
m = 0
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Sub-Routine-Call
Apply Write pulse
Set PV bit in FLMCR1
) µs
Wait (t
spv
H'FF dummy write to verify address
) µs
Wait (t
spvr
Read verify data
Write data =
verify data?
Yes
No
≥
6 n ?
Yes
Additional-programming data computation
Transfer additional-programming data to
additional-programming data area
Reprogram data computation
Transfer reprogram data to reprogram data area
128-byte
data verification completed?
No
Yes
Clear PV bit in FLMCR1
) µs
Wait (t
cpv
No
≥
6 n?
Yes
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse (Additional programming)
No
m = 0 ?
Yes
Clear SWE bit in FLMCR1
) µs
Wait (t
cswe
End of programming
Additional-Programming Data Computation Table
Reprogram Data Verify Data Additional-
(X') (V) Programming Data (Y)
0 0 0
0 1 1
1 0 1
1 1 1
Rev. 6.00 Mar 15, 2006 page 475 of 570
Section 18 ROM
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
7
*
* 4
1
*
See Note *6 for pulse width
* 7
n ← n + 1
* 7
* 2
No
m = 1
* 4
* 3
* 4
* 7
1
*
* 7
No
n ≥ (N)?
Yes
Clear SWE bit in FLMCR1
) µs
Wait (t
*
cswe
Programming failure
Comments
Additional programming to be executed
Additional programming not to be executed
Additional programming not to be executed
Additional programming not to be executed
REJ09B0211-0600
Reprogram
7