Sign In
Upload
Manuals
Brands
Renesas Manuals
Computer Hardware
H8S/2600 Series
Renesas H8S/2600 Series Manuals
Manuals and User Guides for Renesas H8S/2600 Series. We have
2
Renesas H8S/2600 Series manuals available for free PDF download: Hardware Manual, User Manual
Renesas H8S/2600 Series Hardware Manual (609 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 3.18 MB
Table of Contents
Table of Contents
11
Section 1 Overview
37
Overview
37
Internal Block Diagram
39
Figure 1.1 Internal Block Diagram (HD64F2612, HD6432612, and HD6432611)
39
Section 1 Overview
39
Figure 1.2 Internal Block Diagram (HD6432616 and HD6432614)
40
Pin Arrangement
41
Figure 1.3 Pin Arrangement (HD64F2612, HD6432612, and HD6432611)
41
Figure 1.4 Pin Arrangement (HD6432616 and HD6432614)
42
Pin Functions
43
Differences between H8S/2612, H8S/2611, H8S/2614, and H8S/2616
48
Table 1.1 Comparison of Product Specifications
48
Section 2 CPU
49
Features
49
Differences between H8S/2600 CPU and H8S/2000 CPU
50
Section 2 CPU
50
Differences from H8/300 CPU
51
Differences from H8/300H CPU
51
CPU Operating Modes
52
Normal Mode
52
Advanced Mode
53
Figure 2.1 Exception Vector Table (Normal Mode)
53
Figure 2.2 Stack Structure in Normal Mode
53
Figure 2.3 Exception Vector Table (Advanced Mode)
54
Figure 2.4 Stack Structure in Advanced Mode
55
Address Space
56
Figure 2.5 Memory Map
56
Register Configuration
57
Figure 2.6 CPU Registers
57
Figure 2.7 Usage of General Registers
58
General Registers
58
Extended Control Register (EXR)
59
Figure 2.8 Stack
59
Program Counter (PC)
59
Condition-Code Register (CCR)
60
Initial Values of CPU Registers
62
Multiply-Accumulate Register (MAC)
62
Data Formats
63
General Register Data Formats
63
Figure 2.9 General Register Data Formats (1)
63
Figure 2.9 General Register Data Formats (2)
64
Memory Data Formats
65
Figure 2.10 Memory Data Formats
65
Instruction Set
66
Table 2.1 Instruction Classification
66
Table 2.2 Operation Notation
67
Table of Instructions Classified by Function
67
Table 2.3 Data Transfer Instructions
68
Table 2.4 Arithmetic Operations Instructions
69
Table 2.5 Logic Operations Instructions
71
Table 2.6 Shift Instructions
71
Table 2.7 Bit Manipulation Instructions
72
Table 2.8 Branch Instructions
74
Table 2.9 System Control Instructions
75
Basic Instruction Formats
76
Table 2.10 Block Data Transfer Instructions
76
Figure 2.11 Instruction Formats (Examples)
77
Addressing Modes and Effective Address Calculation
78
Register Direct-Rn
78
Register Indirect-@Ern
78
Table 2.11 Addressing Modes
78
Register Indirect with Displacement-@(D:16, Ern) or @(D:32, Ern)
79
Register Indirect with Post-Increment or Pre-Decrement-@Ern+ or @-Ern
79
Absolute Address-@Aa:8, @Aa:16, @Aa:24, or @Aa:32
79
Immediate-#XX:8, #XX:16, or #XX:32
80
Program-Counter Relative-@(D:8, PC) or @(D:16, PC)
80
Memory Indirect-@@Aa:8
80
Table 2.12 Absolute Address Access Ranges
80
Effective Address Calculation
81
Figure 2.12 Branch Address Specification in Memory Indirect Mode
81
Processing States
84
Usage Notes
85
Usage Notes on Bit Manipulation Instructions
85
Figure 2.13 State Transitions
85
Section 3 MCU Operating Modes
87
Operating Mode Selection
87
Register Descriptions
87
Table 3.1 MCU Operating Mode Selection
87
Mode Control Register(MDCR)
88
System Control Register(SYSCR)
89
Pin Functions in each Operating Mode
90
Pin Functions
90
Table 3.2 Pin Functions in each Mode
90
Address Map
91
Figure 3.1 Address Map (H8S/2612, H8S/2611, H8S/2616, H8S/2614)
91
Section 4 Exception Handling
93
Exception Handling Types and Priority
93
Exception Sources and Exception Vector Table
93
Table 4.1 Exception Types and Priority
93
Table 4.2 Exception Handling Vector Table
94
Reset
95
Reset Exception Handling
95
Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled)
96
Interrupts after Reset
97
State of On-Chip Supporting Modules after Reset Release
97
Figure 4.2 Reset Sequence
97
Traces
98
Interrupts
98
Table 4.3 Status of CCR and EXR after Trace Exception Handling
98
Trap Instruction
99
Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling
99
Stack Status after Exception Handling
100
Figure 4.3 Stack Status after Exception Handling
100
Usage Note
101
Figure 4.4 Operation When SP Value Is Odd
101
Section 5 Interrupt Controller
103
Features
103
Figure 5.1 Block Diagram of Interrupt Controller
104
Input/Output Pins
105
Register Descriptions
105
Interrupt Priority Registers a to H, J, K, M (IPRA to IPRH,IPRJ, IPRK, IPRM)
106
IRQ Enable Register (IER)
107
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
107
IRQ Status Register (ISR)
110
Interrupt
111
External Interrupts
111
Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5
111
Internal Interrupts
112
Interrupt Exception Handling Vector Table
112
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities
113
Interrupt Control Modes and Interrupt Operation
115
Interrupt Control Mode 0
115
Table 5.3 Interrupt Control Modes
115
Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control
116
Interrupt Control Mode 2
117
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Control Mode 2
118
Interrupt Exception Handling Sequence
119
Figure 5.5 Interrupt Exception Handling
120
Interrupt Response Times
121
Table 5.4 Interrupt Response Times
121
DTC Activation by Interrupt
122
Usage Notes
122
Contention between Interrupt Generation and Disabling
122
Table 5.5 Number of States in Interrupt Handling Routine Execution Status
122
Instructions that Disable Interrupts
123
When Interrupts Are Disabled
123
Figure 5.6 Contention between Interrupt Generation and Disabling
123
Interrupts During Execution of EEPMOV Instruction
124
Section 6 PC Break Controller (PBC)
125
Features
125
Register Descriptions
126
Break Address Register a (BARA)
126
Figure 6.1 Block Diagram of PC Break Controller
126
Break Address Register B (BARB)
127
Break Control Register a (BCRA)
127
Break Control Register B (BCRB)
128
Operation
128
PC Break Interrupt Due to Instruction Fetch
128
PC Break Interrupt Due to Data Access
128
Notes on PC Break Interrupt Handling
129
Operation in Transitions to Power-Down Modes
129
Figure 6.2 Operation in Power-Down Mode Transitions
129
When Instruction Execution Is Delayed by One State
130
Usage Notes
131
Module Stop Mode Setting
131
PC Break Interrupts
131
CMFA and CMFB
131
PC Break Interrupt When DTC Is Bus Master
131
PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA, RTE, or RTS Instruction
131
I Bit Set by LDC, ANDC, ORC, or XORC Instruction
131
PC Break Set for Instruction Fetch at Address Following Bcc Instruction
132
PC Break Set for Instruction Fetch at Branch Destination Address of Bcc Instruction
132
Section 7 Bus Controller
133
Basic Timing
133
On-Chip Memory Access Timing (ROM, RAM)
133
Figure 7.1 On-Chip Memory Access Cycle
133
On-Chip Support Module Access Timing
134
Figure 7.2 On-Chip Support Module Access Cycle
134
On-Chip HCAN Module Access Timing
135
Figure 7.3 On-Chip HCAN Module Access Cycle (Wait States Inserted)
135
On-Chip MMT Module Access Timing
136
Figure 7.4 On-Chip MMT Module Access Cycle
136
Bus Arbitration
137
Order of Priority of the Bus Masters
137
Bus Transfer Timing
137
Section 8 Data Transfer Controller (DTC)
139
Features
139
Figure 8.1 Block Diagram of DTC
140
Register Configuration
141
DTC Mode Register a (MRA)
142
DTC Mode Register B (MRB)
143
DTC Source Address Register (SAR)
143
DTC Destination Address Register (DAR)
143
DTC Transfer Count Register a (CRA)
143
DTC Transfer Count Register B (CRB)
144
DTC Enable Registers (DTCER)
144
DTC Vector Register (DTVECR)
145
Activation Sources
145
Location of Register Information and DTC Vector Table
146
Figure 8.2 Block Diagram of DTC Activation Source Control
146
Figure 8.3 Correspondence between DTC Vector Address and Register Information
147
Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding Dtces
148
Operation
150
Figure 8.4 Flowchart of DTC Operation
150
Figure 8.5 Memory Mapping in Normal Mode
151
Normal Mode
151
Table 8.2 Register Information in Normal Mode
151
Figure 8.6 Memory Mapping in Repeat Mode
152
Repeat Mode
152
Table 8.3 Register Information in Repeat Mode
152
Block Transfer Mode
153
Table 8.4 Register Information in Block Transfer Mode
153
Figure 8.7 Memory Mapping in Block Transfer Mode
154
Chain Transfer
155
Figure 8.8 Chain Transfer Operation
155
Figure 8.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
156
Interrupts
156
Operation Timing
156
Figure 8.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2)
157
Figure 8.11 DTC Operation Timing (Example of Chain Transfer)
157
Number of DTC Execution States
157
Table 8.5 DTC Execution Status
158
Table 8.6 Number of States Required for each Execution Status
158
Procedures for Using DTC
159
Activation by Interrupt
159
Activation by Software
159
Examples of Use of the DTC
159
Normal Mode
159
Chain Transfer
160
Software Activation
161
Usage Notes
162
Module Stop Mode Setting
162
On-Chip RAM
162
DTCE Bit Setting
162
Section 9 I/O Ports
163
Table 9.1 Port Functions
164
Port 1
166
Port 1 Data Direction Register (P1DDR)
166
Port 1 Data Register (P1DR)
167
Port 1 Register (PORT1)
167
Pin Functions
168
Table 9.2 P17 Pin Function
168
Table 9.3 P16 Pin Function
168
Table 9.4 P15 Pin Function
169
Table 9.5 P14 Pin Function
169
Table 9.6 P13 Pin Function
169
Table 9.7 P12 Pin Function
170
Table 9.8 P11 Pin Function
170
Table 9.9 P10 Pin Function
170
Port 4
171
Port 4 Register (PORT4)
171
Port 9
172
Port 9 Register (PORT9)
172
Port a
173
Port a Data Direction Register (PADDR)
173
Port a Data Register (PADR)
174
Port a Register (PORTA)
174
Port a Pull-Up MOS Control Register (PAPCR)
175
Port a Open-Drain Control Register (PAODR)
175
Pin Functions
176
Table 9.10 PA3 Pin Function
176
Table 9.11 PA2 Pin Function
176
Table 9.12 PA1 Pin Function
176
Table 9.13 PA0 Pin Function
176
Port B
177
Port B Data Direction Register (PBDDR)
177
Port B Data Register (PBDR)
178
Port B Register (PORTB)
178
Port B Pull-Up MOS Control Register (PBPCR)
179
Port B Open-Drain Control Register (PBODR)
179
Pin Functions
180
Table 9.14 PB7 Pin Function
180
Table 9.15 PB6 Pin Function
180
Table 9.16 PB5 Pin Function
181
Table 9.17 PB4 Pin Function
181
Table 9.18 PB3 Pin Function
181
Table 9.19 PB2 Pin Function
182
Table 9.20 PB1 Pin Function
182
Table 9.21 PB0 Pin Function
182
Port C
183
Port C Data Direction Register (PCDDR)
183
Port C Data Register (PCDR)
184
Port C Register (PORTC)
184
Port C Pull-Up MOS Control Register (PCPCR)
185
Port C Open-Drain Control Register (PCODR)
185
Pin Functions
186
Port D
188
Port D Data Direction Register (PDDDR)
188
Port D Data Register (PDDR)
189
Port D Register (PORTD)
189
Port D Pull-Up MOS Control Register (PDPCR)
190
Port F
191
Port F Data Direction Register (PFDDR)
191
Port F Data Register (PFDR)
192
Port F Register (PORTF)
192
Pin Functions
193
Section 10 16-Bit Timer Pulse Unit (TPU)
195
Features
195
Table 10.1 TPU Functions
196
Figure 10.1 Block Diagram of TPU
198
Input/Output Pins
199
Table 10.2 TPU Pins
199
Register Descriptions
200
Timer Control Register (TCR)
202
Table 10.3 CCLR0 to CCLR2 (Channels 0 and 3)
203
Table 10.4 CCLR0 to CCLR2 (Channels 1, 2, 4, and 5)
203
Table 10.5 TPSC0 to TPSC2 (Channel 0)
204
Table 10.6 TPSC0 to TPSC2 (Channel 1)
204
Table 10.7 TPSC0 to TPSC2 (Channel 2)
205
Table 10.8 TPSC0 to TPSC2 (Channel 3)
205
Table 10.9 TPSC0 to TPSC2 (Channel 4)
206
Table 10.10 TPSC0 to TPSC2 (Channel 5)
206
Timer Mode Register (TMDR)
207
Table 10.11 MD0 to MD3
208
Timer I/O Control Register (TIOR)
209
Table 10.12 TIORH_0 (Channel 0)
210
Table 10.13 TIORL_0 (Channel 0)
211
Table 10.14 TIOR_1 (Channel 1)
212
Table 10.15 TIOR_2 (Channel 2)
213
Table 10.16 TIORH_3 (Channel 3)
214
Table 10.17 TIORL_3 (Channel 3)
215
Table 10.18 TIOR_4 (Channel 4)
216
Table 10.19 TIOR_5 (Channel 5)
217
Table 10.20 TIORH_0 (Channel 0)
218
Table 10.21 TIORL_0 (Channel 0)
219
Table 10.22 TIOR_1 (Channel 1)
220
Table 10.23 TIOR_2 (Channel 2)
221
Table 10.24 TIORH_3 (Channel 3)
222
Table 10.25 TIORL_3 (Channel 3)
223
Table 10.26 TIOR_4 (Channel 4)
224
Table 10.27 TIOR_5 (Channel 5)
225
Timer Interrupt Enable Register (TIER)
226
Timer Status Register (TSR)
228
Timer Counter (TCNT)
231
Timer General Register (TGR)
231
Timer Start Register (TSTR)
231
Timer Synchro Register (TSYR)
232
Operation
233
Basic Functions
233
Figure 10.2 Example of Counter Operation Setting Procedure
233
Figure 10.3 Free-Running Counter Operation
234
Figure 10.4 Periodic Counter Operation
235
Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match
235
Figure 10.6 Example of 0 Output/1 Output Operation
236
Figure 10.7 Example of Toggle Output Operation
236
Figure 10.8 Example of Input Capture Operation Setting Procedure
237
Figure 10.9 Example of Input Capture Operation
238
Synchronous Operation
239
Figure 10.10 Example of Synchronous Operation Setting Procedure
239
Figure 10.11 Example of Synchronous Operation
240
Buffer Operation
241
Figure 10.12 Compare Match Buffer Operation
241
Table 10.28 Register Combinations in Buffer Operation
241
Figure 10.13 Input Capture Buffer Operation
242
Figure 10.14 Example of Buffer Operation Setting Procedure
242
Figure 10.15 Example of Buffer Operation (1)
243
Figure 10.16 Example of Buffer Operation (2)
244
Cascaded Operation
245
Figure 10.17 Cascaded Operation Setting Procedure
245
Table 10.29 Cascaded Combinations
245
Figure 10.18 Example of Cascaded Operation (1)
246
Figure 10.19 Example of Cascaded Operation (2)
246
PWM Modes
247
Table 10.30 PWM Output Registers and Output Pins
248
Figure 10.20 Example of PWM Mode Setting Procedure
249
Figure 10.21 Example of PWM Mode Operation (1)
250
Figure 10.22 Example of PWM Mode Operation (2)
250
Figure 10.23 Example of PWM Mode Operation (3)
251
Phase Counting Mode
252
Table 10.31 Phase Counting Mode Clock Input Pins
252
Figure 10.24 Example of Phase Counting Mode Setting Procedure
253
Figure 10.25 Example of Phase Counting Mode 1 Operation
253
Figure 10.26 Example of Phase Counting Mode 2 Operation
254
Table 10.32 Up/Down-Count Conditions in Phase Counting Mode 1
254
Figure 10.27 Example of Phase Counting Mode 3 Operation
255
Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2
255
Figure 10.28 Example of Phase Counting Mode 4 Operation
256
Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 3
256
Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 4
257
Figure 10.29 Phase Counting Mode Application Example
258
Interrupts
259
Table 10.36 TPU Interrupts
260
DTC Activation
261
A/D Converter Activation
261
Operation Timing
262
Input/Output Timing
262
Figure 10.30 Count Timing in Internal Clock Operation
262
Figure 10.31 Count Timing in External Clock Operation
262
Figure 10.32 Output Compare Output Timing
263
Figure 10.33 Input Capture Input Signal Timing
263
Figure 10.34 Counter Clear Timing (Compare Match)
264
Figure 10.35 Counter Clear Timing (Input Capture)
264
Figure 10.36 Buffer Operation Timing (Compare Match)
265
Figure 10.37 Buffer Operation Timing (Input Capture)
265
Interrupt Signal Timing
266
Figure 10.38 TGI Interrupt Timing (Compare Match)
266
Figure 10.39 TGI Interrupt Timing (Input Capture)
267
Figure 10.40 TCIV Interrupt Setting Timing
267
Figure 10.41 TCIU Interrupt Setting Timing
268
Figure 10.42 Timing for Status Flag Clearing by CPU
268
Figure 10.43 Timing for Status Flag Clearing by DTC Activation
269
Usage Notes
270
Module Stop Mode Setting
270
Input Clock Restrictions
270
Caution on Period Setting
270
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
270
Contention between TCNT Write and Clear Operations
271
Figure 10.45 Contention between TCNT Write and Clear Operations
271
Contention between TCNT Write and Increment Operations
272
Figure 10.46 Contention between TCNT Write and Increment Operations
272
Contention between TGR Write and Compare Match
273
Figure 10.47 Contention between TGR Write and Compare Match
273
Contention between Buffer Register Write and Compare Match
274
Figure 10.48 Contention between Buffer Register Write and Compare Match
274
Contention between TGR Read and Input Capture
275
Figure 10.49 Contention between TGR Read and Input Capture
275
Contention between TGR Write and Input Capture
276
Figure 10.50 Contention between TGR Write and Input Capture
276
10.9.10 Contention between Buffer Register Write and Input Capture
277
Figure 10.51 Contention between Buffer Register Write and Input Capture
277
10.9.11 Contention between Overflow/Underflow and Counter Clearing
278
Figure 10.52 Contention between Overflow and Counter Clearing
278
10.9.12 Contention between TCNT Write and Overflow/Underflow
279
10.9.13 Multiplexing of I/O Pins
279
10.9.14 Interrupts in Module Stop Mode
279
Figure 10.53 Contention between TCNT Write and Overflow
279
Section 11 Motor Management Timer (MMT)
281
Features
281
Figure 11.1 Block Diagram of MMT
282
Input/Output Pins
283
Register Descriptions
283
Table 11.1 Pin Configuration
283
Timer Mode Register (TMDR)
284
Timer Control Register (TCNR)
285
Timer Counter (TCNT)
286
Timer Status Register (TSR)
286
Timer Buffer Registers (TBR)
287
Timer Dead Time Counters (TDCNT)
287
Timer Dead Time Data Register (TDDR)
287
Timer General Registers (TGR)
287
Timer Period Buffer Register (TPBR)
287
Timer Period Data Register (TPDR)
287
MMT Pin Control Register (MMTPC)
288
Operation
289
Sample Setting Procedure
290
Figure 11.2 Sample Operating Mode Setting Procedure
290
Figure 11.3 MMT Canceling Procedure
291
Figure 11.4 Example of TCNT Count Operation
292
Figure 11.5 Examples of Counter and Register Operations
293
Table 11.2 Initial Values of TBRU to TBRW and Initial Output
295
Figure 11.6 Example of PWM Waveform Generation
296
Figure 11.7 Example of TCNT Counter Clearing
297
Output Protection Functions
298
Figure 11.8 Example of Toggle Output Waveform Synchronized with PWM Period
298
Interrupts
299
Table 11.3 MMT Interrupt Sources
299
Operation Timing
300
Input/Output Timing
300
Figure 11.9 Count Timing
300
Figure 11.10 TCNT Counter Clearing Timing
300
Figure 11.11 TDCNT Operation Timing
301
Figure 11.12 Dead Time Generation Timing
302
Figure 11.13 Buffer Operation Timing
303
Interrupt Signal Timing
304
Figure 11.14 TGI Interrupt Timing
304
Figure 11.15 Timing of Status Flag Clearing by CPU
305
Figure 11.16 Timing of Status Flag Clearing by DTC Controller
305
Usage Notes
306
Module Stop Mode Setting
306
Notes for MMT Operation
306
Figure 11.17 Contention between Buffer Register Write and Compare Match
306
Figure 11.18 Contention between Compare Register Write and Compare Match
307
Figure 11.19 Error Case in Writing Operation
308
Figure 11.20 Output Waveform Caused by Dead Time Limitation
309
Port Output Enable (POE)
310
Features
310
Figure 11.21 Block Diagram of POE
310
Input/Output Pins
311
Register Descriptions
311
Table 11.4 Pin Configuration
311
Operation
315
Figure 11.22 Low Level Detection Operation
315
Section 12 Programmable Pulse Generator (PPG)
317
Features
317
Figure 12.1 Block Diagram of PPG
318
Input/Output Pins
319
Register Descriptions
319
Table 12.1 PPG I/O Pins
319
Next Data Enable Registers H, L (NDERH, NDERL)
320
Output Data Registers H, L (PODRH, PODRL)
321
Next Data Registers H, L (NDRH, NDRL)
322
PPG Output Control Register (PCR)
325
PPG Output Mode Register (PMR)
326
Operation
327
Overview
327
Figure 12.2 PPG Output Operation
327
Output Timing
328
Figure 12.3 Timing of Transfer and Output of NDR Contents (Example)
328
Sample Setup Procedure for Normal Pulse Output
329
Figure 12.4 Setup Procedure for Normal Pulse Output (Example)
329
Example of Normal Pulse Output (Example of Five-Phase Pulse Output)
330
Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output)
330
Non-Overlapping Pulse Output
331
Figure 12.6 Non-Overlapping Pulse Output
331
Figure 12.7 Non-Overlapping Operation and NDR Write Timing
332
Sample Setup Procedure for Non-Overlapping Pulse Output
333
Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example)
333
Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output)
334
Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)
334
Inverted Pulse Output
336
Figure 12.10 Inverted Pulse Output (Example)
336
Pulse Output Triggered by Input Capture
337
Usage Notes
337
Module Stop Mode Setting
337
Operation of Pulse Output Pins
337
Figure 12.11 Pulse Output Triggered by Input Capture (Example)
337
Section 13 Watchdog Timer
339
Features
339
Register Descriptions
340
Timer Counter (TCNT)
340
Figure 13.1 Block Diagram of WDT
340
Timer Control/Status Register (TCSR)
341
Reset Control/Status Register (RSTCSR)
343
Operation
344
Watchdog Timer Mode
344
Interval Timer Mode
344
Interrupts
345
Usage Notes
345
Notes on Register Access
345
Table 13.1 WDT Interrupt Source
345
Figure 13.2 Writing to TCNT, TCSR, and RSTCSR (Example for WDT0)
346
Contention between Timer Counter (TCNT) Write and Increment
347
Changing Value of CKS2 to CKS0
347
Switching between Watchdog Timer Mode and Interval Timer Mode
347
Figure 13.3 Contention between TCNT Write and Increment
347
Internal Reset in Watchdog Timer Mode
348
OVF Flag Clearing in Intervel Timer Mode
348
Section 14 Serial Communication Interface (SCI)
349
Features
349
Figure 14.1 Block Diagram of SCI
350
Input/Output Pins
351
Register Descriptions
351
Table 14.1 Pin Configuration
351
Receive Data Register (RDR)
352
Receive Shift Register (RSR)
352
Transmit Data Register (TDR)
352
Transmit Shift Register (TSR)
352
Serial Mode Register (SMR)
353
Serial Control Register (SCR)
357
Serial Status Register (SSR)
360
Smart Card Mode Register (SCMR)
366
Bit Rate Register (BRR)
367
Table 14.2 Relationships between the N Setting in BRR and Bit Rate B
367
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode)
368
Table 14.4 Maximum Bit Rate for each Frequency (Asynchronous Mode)
370
Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
371
Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
372
Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
372
Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (When N = 0 and S = 372)
373
Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
373
Operation in Asynchronous Mode
374
Data Transfer Format
374
Figure 14.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)
374
Table 14.10 Serial Transfer Formats (Asynchronous Mode)
375
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
376
Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode
376
Clock
377
Figure 14.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode)
377
SCI Initialization (Asynchronous Mode)
378
Figure 14.5 Sample SCI Initialization Flowchart
378
Data Transmission (Asynchronous Mode)
379
Figure 14.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
379
Figure 14.7 Sample Serial Transmission Flowchart
380
Serial Data Reception (Asynchronous Mode)
381
Figure 14.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit)
381
Table 14.11 SSR Status Flags and Receive Data Handling
382
Figure 14.9 Sample Serial Reception Data Flowchart (1)
383
Figure 14.9 Sample Serial Reception Data Flowchart (2)
384
Multiprocessor Communication Function
385
Multiprocessor Serial Data Transmission
386
Figure 14.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
386
Figure 14.11 Sample Multiprocessor Serial Transmission Flowchart
387
Multiprocessor Serial Data Reception
388
Figure 14.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
388
Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (1)
389
Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2)
390
Operation in Clocked Synchronous Mode
391
Clock
391
Figure 14.14 Data Format in Synchronous Communication (for LSB-First)
391
SCI Initialization (Clocked Synchronous Mode)
392
Figure 14.15 Sample SCI Initialization Flowchart
392
Serial Data Transmission (Clocked Synchronous Mode)
393
Figure 14.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
394
Figure 14.17 Sample Serial Transmission Flowchart
395
Serial Data Reception (Clocked Synchronous Mode)
396
Figure 14.18 Example of SCI Operation in Reception
396
Figure 14.19 Sample Serial Reception Flowchart
397
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
398
Figure 14.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
399
Operation in Smart Card Interface
400
Pin Connection Example
400
Figure 14.21 Schematic Diagram of Smart Card Interface Pin Connections
400
Data Format (Except for Block Transfer Mode)
401
Figure 14.22 Normal Smart Card Interface Data Format
401
Figure 14.23 Direct Convention (SDIR = SINV = O/E = 0)
401
Block Transfer Mode
402
Figure 14.24 Inverse Convention (SDIR = SINV = O/E = 1)
402
Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode
403
Initialization
404
Figure 14.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate)
404
Data Transmission (Except for Block Transfer Mode)
405
Figure 14.26 Retransfer Operation in SCI Transmit Mode
406
Figure 14.27 TEND Flag Generation Timing in Transmission Operation
406
Figure 14.28 Example of Transmission Processing Flow
407
Serial Data Reception (Except for Block Transfer Mode)
408
Figure 14.29 Retransfer Operation in SCI Receive Mode
408
Figure 14.30 Example of Reception Processing Flow
409
Clock Output Control
410
Figure 14.31 Timing for Fixing Clock Output Level
410
Interrupts
411
Interrupts in Normal Serial Communication Interface Mode
411
Figure 14.32 Clock Halt and Restart Procedure
411
Interrupts in Smart Card Interface Mode
412
Table 14.12 SCI Interrupt Sources
412
Table 14.13 SCI Interrupt Sources
412
Usage Notes
414
Module Stop Mode Setting
414
Break Detection and Processing
414
Mark State and Break Detection
414
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
414
Restrictions on Using DTC
415
SCI Operations During Mode Transitions
415
Figure 14.33 Sample Transmission Using DTC in Clocked Synchronous Mode
415
Figure 14.34 Sample Flowchart for Mode Transition During Transmission
416
Figure 14.35 Pin States During Transmission in Asynchronous Mode (Internal Clock)
416
Figure 14.36 Pin States During Transmission in Clocked Synchronous Mode
417
Notes When Switching from SCK Pin to Port Pin
418
Figure 14.37 Sample Flowchart for Mode Transition During Reception
418
Figure 14.38 Operation When Switching from SCK Pin to Port Pin
419
Section 15 Controller Area Network (HCAN)
421
Features
421
Figure 15.1 HCAN Block Diagram
422
Input/Output Pins
423
Register Descriptions
423
Table 15.1 HCAN Pins
423
Master Control Register (MCR)
424
General Status Register (GSR)
425
Bit Configuration Register (BCR)
427
Mailbox Configuration Register (MBCR)
429
Transmit Wait Register (TXPR)
430
Transmit Wait Cancel Register (TXCR)
431
Transmit Acknowledge Register (TXACK)
432
Abort Acknowledge Register (ABACK)
433
Receive Complete Register (RXPR)
434
Remote Request Register (RFPR)
435
Interrupt Register (IRR)
436
Mailbox Interrupt Mask Register (MBIMR)
440
Interrupt Mask Register (IMR)
441
Receive Error Counter (REC)
442
Transmit Error Counter (TEC)
442
Unread Message Status Register (UMSR)
443
Local Acceptance Filter Masks (LAFML, LAFMH)
444
Figure 15.2 Message Control Register Configuration
447
Figure 15.3 Standard Format
447
Figure 15.4 Extended Format
447
Message Control (MC0 to MC15)
447
Figure 15.5 Message Data Configuration
449
Message Data (MD0 to MD15)
449
HCAN Monitor Register (HCANMON)
450
Operation
451
Hardware and Software Resets
451
Initialization after Hardware Reset
451
Figure 15.6 Hardware Reset Flowchart
452
Figure 15.7 Software Reset Flowchart
453
Figure 15.8 Detailed Description of One Bit
454
Table 15.2 Limits for Settable Value
454
Table 15.3 Setting Range for TSEG1 and TSEG2 in BCR
455
Message Transmission
457
Figure 15.9 Transmission Flowchart
457
Figure 15.10 Transmit Message Cancellation Flowchart
459
Message Reception
460
Figure 15.11 Reception Flowchart
460
HCAN Sleep Mode
463
Figure 15.12 Unread Message Overwrite Flowchart
463
Figure 15.13 HCAN Sleep Mode Flowchart
464
HCAN Halt Mode
466
Figure 15.14 HCAN Halt Mode Flowchart
466
Interrupts
467
Table 15.4 HCAN Interrupt Sources
467
DTC Interface
468
Figure 15.15 DTC Transfer Flowchart
468
CAN Bus Interface
469
Usage Notes
469
Module Stop Mode Setting
469
Reset
469
Figure 15.16 High-Speed Interface Using PCA82C250
469
HCAN Sleep Mode
470
Interrupts
470
Error Counters
470
Register Access
470
HCAN Medium-Speed Mode
470
Register Hold in Standby Modes
470
Usage of Bit Manipulation Instructions
470
15.8.10 HCAN TXCR Operation
471
Section 16 A/D Converter
473
Features
473
Figure 16.1 Block Diagram of A/D Converter
474
Input/Output Pins
475
Table 16.1 Pin Configuration
475
Register Description
476
A/D Data Registers a to D (ADDRA to ADDRD)
476
A/D Control/Status Register (ADCSR)
477
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
477
A/D Control Register (ADCR)
479
Operation
480
Single Mode
480
Scan Mode
480
Input Sampling and A/D Conversion Time
481
Figure 16.2 A/D Conversion Timing
481
Table 16.3 A/D Conversion Time (Single Mode)
482
Table 16.4 A/D Conversion Time (Scan Mode)
482
External Trigger Input Timing
483
Interrupts
483
Figure 16.3 External Trigger Input Timing
483
Table 16.5 A/D Converter Interrupt Source
483
A/D Conversion Precision Definitions
484
Figure 16.4 A/D Conversion Precision Definitions
485
Figure 16.5 A/D Conversion Precision Definitions
485
Usage Notes
486
Module Stop Mode Setting
486
Permissible Signal Source Impedance
486
Influences on Absolute Precision
486
Figure 16.6 Example of Analog Input Circuit
486
Range of Analog Power Supply and Other Pin Settings
487
Notes on Board Design
487
Notes on Noise Countermeasures
487
Figure 16.7 Example of Analog Input Protection Circuit
488
Figure 16.8 Analog Input Pin Equivalent Circuit
488
Table 16.6 Analog Pin Specifications
488
Section 17 RAM
489
Section 18 ROM
491
Features
491
Mode Transitions
492
Figure 18.1 Block Diagram of Flash Memory
492
Figure 18.2 Flash Memory State Transitions
493
Table 18.1 Differences between Boot Mode and User Program Mode
493
Figure 18.3 Boot Mode
494
Figure 18.4 User Program Mode
495
Block Configuration
496
Figure 18.5 Flash Memory Block Configuration
496
Input/Output Pins
497
Table 18.2 Pin Configuration
497
Register Descriptions
498
Flash Memory Control Register 1 (FLMCR1)
498
Flash Memory Control Register 2 (FLMCR2)
500
Erase Block Register 1 (EBR1)
500
Erase Block Register 2 (EBR2)
501
RAM Emulation Register (RAMER)
501
On-Board Programming Modes
502
Table 18.3 Setting On-Board Programming Modes
502
Boot Mode
503
Table 18.4 Boot Mode Operation
504
Table 18.5 System Clock Frequencies for Which Automatic Adjustment of LSI Bit Rate Is
504
Programming/Erasing in User Program Mode
505
Figure 18.6 Programming/Erasing Flowchart Example in User Program Mode
506
Flash Memory Emulation in RAM
507
Figure 18.7 Flowchart for Flash Memory Emulation in RAM
507
Figure 18.8 Example of RAM Overlap Operation
508
Flash Memory Programming/Erasing
509
Program/Program-Verify
509
Figure 18.9 Program/Program-Verify Flowchart
511
Erase/Erase-Verify
512
Interrupt Handling When Programming/Erasing Flash Memory
512
Figure 18.10 Erase/Erase-Verify Flowchart
513
Program/Erase Protection
514
Hardware Protection
514
Software Protection
514
Error Protection
514
Programmer Mode
515
Power-Down States for Flash Memory
515
Table 18.6 Flash Memory Operating States
515
Note on Switching from F-ZTAT Version to Mask ROM Version
516
Table 18.7 Registers Present in F-ZTAT Version but Absent in Mask ROM Version
516
Section 19 Clock Pulse Generator
517
Figure 19.1 Block Diagram of Clock Pulse Generator
517
Register Descriptions
518
System Clock Control Register (SCKCR)
518
Low-Power Control Register (LPWRCR)
519
Oscillator
520
Connecting a Crystal Resonator
520
Figure 19.2 Connection of Crystal Resonator (Example)
520
Figure 19.3 Crystal Resonator Equivalent Circuit
520
Table 19.1 Damping Resistance Value
520
External Clock Input
521
Figure 19.4 External Clock Input (Examples)
521
Table 19.2 Crystal Resonator Characteristics
521
Figure 19.5 External Clock Input Timing
522
Table 19.3 External Clock Input Conditions
522
PLL Circuit
523
Medium-Speed Clock Divider
523
Bus Master Clock Selection Circuit
523
Usage Notes
524
Note on Crystal Resonator
524
Note on Board Design
524
Figure 19.6 Note on Board Design of Oscillator Circuit
524
Figure 19.7 External Circuitry Recommended for PLL Circuit
525
Section 20 Power-Down Modes
527
Table 20.1 Low Power Dissipation Mode Transition Conditions
527
Figure 20.1 Mode Transition Diagram
528
Table 20.2 LSI Internal States in each Mode
529
Register Descriptions
530
Standby Control Register (SBYCR)
530
Module Stop Control Registers a to C (MSTPCRA to MSTPCRC)
532
Medium-Speed Mode
533
Figure 20.2 Medium-Speed Mode Transition and Clearance Timing
534
Sleep Mode
535
Transition to Sleep Mode
535
Clearing Sleep Mode
535
Software Standby Mode
536
Transition to Software Standby Mode
536
Clearing Software Standby Mode
536
Setting Oscillation Stabilization Time after Clearing Software Standby Mode
537
Table 20.3 Oscillation Stabilization Time Settings
537
Software Standby Mode Application Example
538
Figure 20.3 Software Standby Mode Application Example
538
Hardware Standby Mode
539
Transition to Hardware Standby Mode
539
Clearing Hardware Standby Mode
539
Hardware Standby Mode Timings
539
Figure 20.4 Timing of Transition to Hardware Standby Mode
539
Module Stop Mode
540
Figure 20.5 Timing of Recovery from Hardware Standby Mode
540
Clock Output Disabling Function
541
Table 20.4 Φ Pin State in each Processing State
541
Usage Notes
542
I/O Port Status
542
Current Dissipation During Oscillation Stabilization Wait Period
542
DTC Module Stop
542
On-Chip Supporting Module Interrupt
542
Writing to MSTPCR
542
Section 21 Electrical Characteristics
543
Absolute Maximum Ratings
543
Table 21.1 Absolute Maximum Ratings
543
DC Characteristics
544
Table 21.2 DC Characteristics
544
AC Characteristics
547
Figure 21.1 Output Load Circuit
547
Table 21.3 Permissible Output Currents
547
Clock Timing
548
Figure 21.2 System Clock Timing
548
Table 21.4 Clock Timing
548
Control Signal Timing
549
Figure 21.3 Oscillation Stabilization Timing
549
Table 21.5 Control Signal Timing
549
Figure 21.4 Reset Input Timing
550
Figure 21.5 Interrupt Input Timing
550
Table 21.6 Timing of On-Chip Supporting Modules
551
Timing of On-Chip Supporting Modules
551
Figure 21.6 I/O Port Input/Output Timing
552
Figure 21.7 TPU Input/Output Timing
553
Figure 21.8 TPU Clock Input Timing
553
Figure 21.9 SCK Clock Input Timing
553
Figure 21.10 SCI Input/Output Timing (Clock Synchronous Mode)
554
Figure 21.11 A/D Converter External Trigger Input Timing
554
Figure 21.12 HCAN Input/Output Timing
554
Figure 21.13 PPG Output Timing
554
Figure 21.14 MMT Input/Output Timing
555
Figure 21.15 POE Input/Output Timing
555
A/D Conversion Characteristics
556
Table 21.7 A/D Conversion Characteristics
556
Flash Memory Characteristics
557
Table 21.8 Flash Memory Characteristics
557
Appendix
559
On-Chip I/O Register
559
Register Addresses
559
Register Bits
575
Register States in each Operating Mode
589
I/O Port States in each Pin State
600
Product Code Lineup
601
Package Dimensions
602
Index
603
Advertisement
Renesas H8S/2600 Series User Manual (34 pages)
H8S/2635 FP-128 User System Interface Cable
Brand:
Renesas
| Category:
Computer Hardware
| Size: 0.55 MB
Table of Contents
Important Information
7
Limited Warranty
8
Table of Contents
13
Section 1 Configuration
14
Section 2 Connection Procedures
17
Connecting User System Interface Cable to Emulator Station
17
Connecting User System Interface Cable to User System
19
Installing IC Socket
19
Soldering IC Socket
20
Inserting Cable Head
20
Fastening Cable Head
21
Fastening Cable Body
23
Recommended Dimensions for User System Mount Pad
24
Dimensions for User System Interface Cable Head
25
Resulting Dimensions after Connecting User System Interface Cable
26
Section 3 Installing the MCU on the User System
27
Section 4 Verifying Operation
29
Section 5 Notice
30
Advertisement
Related Products
Renesas H8S/2643 Series
Renesas H8S/2668 Series
Renesas H8S/2678R Series
Renesas H8S/2615 Series
Renesas H8S/2646 Series
Renesas H8S/2655 Series
Renesas H8S/2612 Series
Renesas H8S/2632
Renesas H8S/2633R F-ZTAT
Renesas 32176
Renesas Categories
Computer Hardware
Motherboard
Microcontrollers
Adapter
Switch
More Renesas Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL