Timer Control Register (Tcnr) - Renesas H8S Series Hardware Manual

11.3.2

Timer Control Register (TCNR)

The timer control register (TCNR) controls the enabling or disabling of interrupt requests, selects
the enabling or disabling of register access, selects counter operation or halting, and controls the
enabling or disabling of toggle output synchronized with the PWM period.
Bit Bit Name Initial Value
7 — 0
6 CST 0
5 RPRO 0
4 to 2 — All 0
1 TGIEN 0
0 TGIEM 0
Section 11 Motor Management Timer (MMT)
R/W Description
R/W Reserved
This bit is always read as 0. Only 0 should be written
to this bit.
R/W Timer Counter Start
Selects operation or halting of the timer counter
(TCNT) and timer dead time counter (TDCNT).
0: TCNT and TDCNT operation is halted
1: TCNT and TDCNT perform count operations
R/W Register Protect
Enables or disables the reading of registers other
than TSR, and enables or disables writes to registers
other than TBRU to TBRW, TPBR, and TSR. Writes
to TCNR itself are also disabled. Note that reset
input is necessary in order to write to these registers
again.
0: Register access enabled
1: Register access disabled
— Reserved
These bits are always read as 0. Only 0 should be
written to these bits.
R/W TGR Interrupt Enable N
Enables or disables interrupt requests by the TGFN
bit when TGFN is set to 1 in the TSR register.
0: Interrupt requests by TGFN bit disabled
1: Interrupt requests by TGFN bit enabled
R/W TGR Interrupt Enable M
Enables or disables interrupt requests by the TGFM
bit when TGFM is set to 1 in the TSR register.
0: Interrupt requests by TGFM bit disabled
1: Interrupt requests by TGFM bit enabled
Rev. 6.00 Mar 15, 2006 page 249 of 570
REJ09B0211-0600