Section 17 Ram - Renesas H8S Series Hardware Manual

Section 17 RAM

Section 17 RAM
This LSI has 4 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a
16-bit data bus, enabling one-state access by the CPU to both byte data and word data.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on the system control register (SYSCR), refer to section 3.2.2,
System Control Register (SYSCR).
Note: No DTC is implemented in the H8S/2614 and H8S/2616.
Rev. 6.00 Mar 15, 2006 page 453 of 570
REJ09B0211-0600