Renesas H8S Series Hardware Manual page 61

Bit Bit Name
7 I
6 UI
5 H
4 U
3 N
2 Z
1 V
Initial Value R/W
1 R/W
undefined R/W
undefined R/W
undefined R/W
undefined R/W
undefined R/W
undefined R/W
Description
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI
is accepted regardless of the I bit setting. The I bit is
set to 1 by hardware at the start of an exception-
handling sequence. For details, refer to section 5,
Interrupt Controller.
User Bit or Interrupt Mask Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions. This bit
cannot be used as an interrupt mask bit in this LSI.
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B,
CMP.B, or NEG.B instruction is executed, this flag is
set to 1 if there is a carry or borrow at bit 3, and
cleared to 0 otherwise. When the ADD.W, SUB.W,
CMP.W, or NEG.W instruction is executed, the H
flag is set to 1 if there is a carry or borrow at bit 11,
and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed,
the H flag is set to 1 if there is a carry or borrow at
bit 27, and cleared to 0 otherwise.
User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
Negative Flag
Stores the value of the most significant bit of data as
a sign bit.
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
Rev. 6.00 Mar 15, 2006 page 25 of 570
Section 2 CPU
REJ09B0211-0600