Reset; Figure 28-3. Signal Connections Within The Enhanced Gpio Port Control Logic (Ports A, B, F) - Cirrus Logic EP93 Series User Manual

Enhanced GPIO Ports A, B, and F
to PRDATA[7:0]
Figure 28-3. Signal Connections Within the Enhanced GPIO Port Control Logic

28.1.3 Reset

All GPIO registers are initialized on system reset. The data and data direction registers for all
ports (except as noted below) are cleared, configuring them as inputs. Port E[1:0] bits are
used for the LED outputs RDLED and GRLED respectively and are set to drive high. Port
G[3:2] bits are used for SLA[1:0] outputs and are set to drive low. Port G[1:0] bits are used
for EEDAT and EECLK respectively and are set up as inputs. All interrupt control and
debounce registers are cleared.
DS785UM1
DDR
OE
DR DATA
TISR
OE
Register
Read
Select
DB
OE
INTEN
ENA
INTTYPE1
EDGE
INTTYPE2
POL
(Ports A, B, F)
Copyright 2007 Cirrus Logic
OE[7:0]
DATA[7:0]
TESTRDSEL
TESTINPSEL
1
1
0
0
INTERRUPT
CONTROL
LOGIC
GPIO Interface
EP93xx User's Guide
EP[7:0]
IN
ICLK
CLK
28-5
28