Registers; Table 5-5. Syscon Register List - Cirrus Logic EP93 Series User Manual

5.2 Registers

This section contains the detailed register descriptions for registers in the Syscon block.
Table 5-5 shows the address map for the registers in this block, followed by a detailed listing
for each register.
Address Name
0x8093_0000 PwrSts
0x8093_0004 PwrCnt
0x8093_0008 Halt
0x8093_000C Standby
0x8093_0018 TEOI
0x8093_001C STFClr
0x8093_0020 ClkSet1
0x8093_0024 ClkSet2
0x8093_0040 ScratchReg0
0x8093_0044 ScratchReg1
0x8093_0050 APBWait
0x8093_0054 BusMstrArb
0x8093_0058 BootModeClr
0x8093_0080 DeviceCfg
0x8093_0084 VidClkDiv
0x8093_0088 MIRClkDiv
0x8093_008C I2SClkDiv
0x8093_0090 KeyTchClkDiv
0x8093_0094 ChipID
0x8093_009C SysCfg
0x8093_00A0 -
0x8093_00C0 SysSWLock
DS785UM1

Table 5-5. Syscon Register List

SW Locked Type
No R
No R/W
No R
No R
No W
No W
No R/W
No R/W
No R/W
No R/W
No R/W
No R/W
No W
Yes R/W
Yes R/W
Yes R/W
Yes R/W
Yes R/W
Yes R/W
Yes R/W
- -
No R/W
Copyright 2007 Cirrus Logic
EP93xx User's Guide
Size Description
32 Power/state control state
32 Clock/Debug control status
32 Reading this location enters Halt mode.
32 Reading this location enters Standby mode.
32 Write to clear Tick interrupt
Write to clear CLDFLG, RSTFLG and
32
WDTFLG.
32 Clock speed control 1
32 Clock speed control 2
32 Scratch register 0
32 Scratch register 1
32 APB wait
32 Bus Master Arbitration
32 Boot Mode Clear register
32 Device configuration
32 Video Clock Divider
MIR Clock Divider, divides MIR clock for
32
MIR IrDA
2
32
I S Audio Clock Divider
32 Keyscan/Touch Clock Divider
32 Chip ID Register
32 System Configuration
- Reserved
1 bit Software Lock Register
System Controller
5
5-13