Cirrus Logic EP93 Series User Manual page 393

TDST:
MaxFrmLen
31 30 29 28
RSVD
15 14 13 12
RSVD
Address:
0x8001_00E8 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Maximum Frame Length and Transmit Start Threshold register.
Bit Descriptions:
RSVD:
MFL:
DS785UM1
Transmit Descriptor Soft Threshold.
The hard and soft threshold work in exactly the same
manner except one. The soft threshold will not cause a
bus request to be made if the bus is currently in use, but
only when it is deemed to be idle (no transfers for four
AHB clocks). The hard threshold takes effect immediately
regardless of the state of the bus. This operation allows for
more efficient use of the AHB bus by allowing smaller
transfers to take place when the bus is lightly loaded and
requesting larger transfers only when the bus is more
heavily loaded.
27 26 25 24
11 10 9 8
Reserved. Unknown During Read.
Maximum Frame Length. The maximum frame length is a
limit for the amount of data permitted to be transferred
across the AHB bus for a transmit frame, or on the wire for
a receive frame. When this limit is reached for a transmit
frame, the Transmit Descriptor Processor is halted and a
transmit length error is set in the Interrupt Status register.
When the limit is reached for a receive frame, no further
data will be transferred to memory for the current frame.
The status written for the frame will indicate the length
error, and further frames will continue as normal, (the
Receive Descriptor Processor will not halt).
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
23 22 21 20
MFL
7 6 5 4
TST
EP93xx User's Guide
19 18 17 16
3 2 1 0
9-91
9