Registers; Table 8-22. Graphics Accelerator Registers - Cirrus Logic EP93 Series User Manual

Graphics Accelerator
EP93xx User's Guide

8.7 Registers

8
Address
0x8004_0000
0x8004_0004
0x8004_0008
0x8004_000C
0x8004_0010
0x8004_0014
0x8004_0018
0x8004_001C
0x8004_0020
0x8004_0024
0x8004_0028
0x8004_002C
0x8004_0030
0x8004_0034
0x8004_0038
0x8004_003C
Note: Graphics Accelerator registers are intended to be word accessed only. Since the least
significant bytes of the address bus are not decoded, byte and half word accesses are
illegal and may yield unpredictable results.
8-22

Table 8-22. Graphics Accelerator Registers

SW
Name
locked
"SRCPIXELSTRT" No
"DESTPIXELSTRT" No
"BLKSRCSTRT" No
"BLKDESTSTRT" No
"BLKSRCWIDTH" No
SRCLINELENGTH"S
No
RCLINELENGTH"
"BLKDESTWIDTH" No
"BLKDESTHEIGHT" No
"DESTLINELENGTH" No
"BLOCKCTRL" No
"TRANSPATTRN" No
"BLOCKMASK" No
"BACKGROUND" No
"LINEINC" No
"LINEINIT" No
"LINEPATTRN" No
Copyright 2007 Cirrus Logic
Type Size
Read/Write 5 bits
Read/Write 5 + 5 bits
Read/Write 32 bits Block Source Word Address Start Register
Read/Write 32 bits Block Destination Word Address Start Register
Read/Write 12 bits Block Function Source Width Register
Read/Write 12 bits
Read/Write 12 bits Block Function Destination Width Register
Read/Write 11 bits Block Function Destination Height Register
Read/Write 12 bits
Read/Write 16 bits
Read/Write 24 bits Block Function Transparency Register
Read/Write 24 bits
Read/Write 24 bits
Read/Write 12 + 12 bits
Read/Write 12 + 12 bits
Read/Write 20 bits
Description
Source Pixel Start Register
Destination Pixel Start/End Register
Block Source Line Length Register
Destination Line Length Register
Block Function Control Register
Block Function Mask Register
Block Function Background Register
Line Draw Increment Register
Line Draw Initialization Register
Line Pattern Register
DS785UM1