Cirrus Logic EP93 Series User Manual page 627

DMAERR:
TXDMAE:
RXDMAE:
SIRTR0
31 30 29 28
15 14 13 12
Address:
0x808B_0030 - Read/Write
Default:
0x0000_0000, except that bit 4 is unknown at reset
Definition:
IrDA Slow InfraRed Test Register 0.
Bit Descriptions:
RSVD:
SIREN:
SIROUT:
TXD:
RXD:
DS785UM1
RX DMA error handing enable. If 0, the RX DMA interface
ignores error conditions in the IrDA receive section. If "1",
the DMA interface stops and notifies the DMA block when
an error occurs. Errors include framing errors, receive
abort, and CRC mismatch.
TX DMA interface enable. Setting to "1" enables the
private DMA interface to the transmit FIFO.
RX DMA interface enable. Setting to "1" enables the
private DMA interface to the receive FIFO.
27 26 25
11 10 9
RSVD
Reserved. Unknown During Read.
The state of the SIREN after synchronization. Read only.
The state of SIROUT output from the InfraRed block. Read
only.
The state of the TXD input to the InfraRed block from
UART2. Read only.
The state of the RXD output from the InfraRed block to
UART2. Read only.
Copyright 2007 Cirrus Logic
24 23 22 21
RSVD
8 7 6 5
SIREN SIROUT TXD
EP93xx User's Guide
20 19 18 17
4 3 2 1
RXD SIRT SIRIN S16CLK
IrDA
17
16
0
TSIRC
17-31