Cirrus Logic EP93 Series User Manual page 172

Vectored Interrupt Controller
EP93xx User's Guide
Definition:
6
Bit Descriptions:
VICxFIQStatus
31 30
15 14
Address:
Definition:
Bit Descriptions:
VICxRawIntr
31 30
15 14
Address:
6-10
IRQ Status Register. The VICxIRQStatus register provides the status of
interrupts after IRQ masking.
Interrupts 0 - 31 are in VIC1IRQStatus.
Interrupts 32 - 63 are in VIC2IRQStatus.
IRQStatus:
29 28 27 26
13 12 11 10
VIC1FIQStatus: 0x800B_0004 - Read Only
VIC2FIQStatus: 0x800C_0004 - Read Only
FIQ Status Register. The VICxFIQStatus register provides the status of the
interrupts after FIQ masking.
FIQStatus:
29 28 27 26
13 12 11 10
VIC1RawIntr: 0x800B_0008 - Read Only
VIC2RawIntr: 0x800C_0008 - Read Only
Copyright 2007 Cirrus Logic
Shows the status of the interrupts after masking by the
VICxIntEnable and VICxIntSelect registers. A "1" indicates
that the interrupt is active, and generates an interrupt to
the ARM Core.
25 24 23 22
FIQStatus
9 8 7 6
FIQStatus
Shows the status of the interrupts after masking by the
VICxIntEnable and VICxIntSelect registers. A "1" indicates
that the interrupt is active, and generates an interrupt to
the ARM Core.
25 24 23 22
RawIntr
9 8 7 6
RawIntr
21 20 19 18
5 4 3 2
21 20 19 18
5 4 3 2
17 16
1 0
17 16
1 0
DS785UM1