Internal Register Map; Memory Access Rules; Table 2-8. Internal Register Map - Cirrus Logic EP93 Series User Manual

Note: The shaded memory areas are dedicated to system registers. Details of these registers
are in Table

2.3.6 Internal Register Map

Table 2-8 on page 2-17
their default state by the
registers are reset only by the
specified.

2.3.6.1 Memory Access Rules

Any memory address not specifically assigned to a register should be avoided. Reads to
register memory addresses labelled Reserved, Unused or Undefined will return
indeterminate data. Writes to register memory addresses labelled Reserved, Unused or
Undefined are generally ignored, but this behavior is not guaranteed. Many register
addresses are not fully decoded, so aliasing may occur. Addresses and memory ranges
listed as Reserved (RSVD) should not be accessed; behavior resulting from accesses to
these regions is not defined.
The SW Lock field identifies registers with a software lock. A software lock prevents the
register from being written (unless an unlock operation is performed immediately prior to the
write). Any register whose accidental alteration could cause system damage may be
controlled with a software lock. Each peripheral with software lock capability has its own
software lock register.
Within a register definition, a reserved bit indicated by the name RSVD, means the bit is not
accessible. Software should mask the RSVD bits when doing bit reads. RSVD bits will ignore
writes, that is writing a zero or a one has no affect.
Register bits identified as NC are functionally alive but have an undocumented or a "don't
care" operating function. Bits identified as NC must be treated in a specific manner for reads
and writes. The register descriptions will provide information on how to handle NC bits.
Unless specified otherwise, all registers can be accessed as a byte, half-word, or word.
CAUTION: Some memory locations are listed as Reserved. These memory locations
should not be accessed. Reading from these memory locations will yield invalid data.
Writing to these memory locations may cause unpredictable results.
Address
0x8000_xxxx
0x8000_0000 - 0x8000_003C
0x8000_0040 - 0x8000_007C
0x8000_0080 - 0x8000_00BC
0x8000_00C0 - 0x8000_00FC M2P Channel 3 Registers (Rx) Memory-to-Peripheral Channel 3 Registers (Rx)
0x8000_0100 - 0x8000_013C
DS785UM1
2-8.
shows the memory map for internal registers. Registers are set to
pin input or by the
RSTOn
pin. All registers are read/write unless otherwise
PRSTn

Table 2-8. Internal Register Map

Register Name
DMA
M2P Channel 0 Registers (Tx)
M2P Channel 1 Registers (Rx) Memory-to-Peripheral Channel 1 Registers (Rx)
M2P Channel 2 Registers (Tx)
M2M Channel 0 Registers
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
pin input. Some state conserving
PRSTn
Register Description
DMA Control Registers
Memory-to-Peripheral Channel 0 Registers (Tx)
Memory-to-Peripheral Channel 2 Registers (Tx)
Memory-to-Memory Channel 0 Registers
EP93xx User's Guide
SW
Lock
N
N
N
N
N
2-17
2