Mbps Fir Frame Format; Figure 17-3. 4Ppm Modulation Example; Figure 17-4. Irda (4.0 Mbps) Transmission Format - Cirrus Logic EP93 Series User Manual

Arm 9 embedded processor family
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Receive data sample counter frequency = 6x pulse width, each time-slot sampled on third clock.

17.5.1.2 4.0 Mbps FIR Frame Format

When the 4.0 Mbps transmission rate is used, the high-speed serial/parallel (FIR) interface
within the FIR is used along with the 4PPM bit encoding. The high-speed frame format shown
in
Figure
17-4, is similar to the SDLC format with several minor modifications: the start/stop
flags and CRC are twice as long and instead of one start flag, a preamble and start flag of
differing length are used.
64
symbols
Preamble
DS785UM1

Figure 17-3. 4PPM Modulation Example

8
4 DDs
4 DDs
symbols
(8 bits)
(8 bits)
Control
Start Flag
Address
(optional)
Start Flag
|0000|1100|0000|1100|0110|0000|0110|0000|
|0000|1100|0000|1100|0000|0110|0000|0110|
Preamble
|1000|0000|1010|1000|... repeated 16 times

Figure 17-4. IrDA (4.0 Mbps) Transmission Format

Copyright 2007 Cirrus Logic
8180 DDs max
16 DDs
(2045 bytes)
(32 bits)
Data
CRC-32
IrDA
EP93xx User's Guide
8 symbols
Stop Flag
Stop Flag
17-15
17

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