Cirrus Logic EP93 Series User Manual page 676

2
I S Controller
EP93xx User's Guide
Definition:
Bit Descriptions:
I2SRX0Rt
21
31 30
15 14
Address:
Default:
Definition:
Bit Descriptions:
I2SRX1Lft
31 30
15 14
Address:
Default:
Definition:
Bit Descriptions:
21-20
0x0000_0000
Receive left data word for channel 0.
i2s_rx0_left:
29 28 27 26
13 12 11 10
0x8082_0044 - Read Only
0x0000_0000
Receive right data word for channel 0.
i2s_rx0_right:
29 28 27 26
13 12 11 10
0x8082_0048 - Read Only
0x0000_0000
Receive left data word for channel 1.
i2s_rx1_left:
Copyright 2007 Cirrus Logic
Receive left data word for channel 0.
25 24 23 22
i2s_rx0_right
9 8 7 6
i2s_rx0_right
Receive right data word for channel 0.
25 24 23 22
i2s_rx1_left
9 8 7 6
i2s_rx1_left
Receive left data word for channel 1.
21 20 19 18
5 4 3 2
21 20 19 18
5 4 3 2
17 16
1 0
17 16
1 0
DS785UM1